ADSP-BF538F(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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ADSP-BF538F
(Rev.:Rev0)

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF538/ADSP-BF538F

TABLE OF CONTENTS

General Description ................................................. 3

Low Power Architecture ......................................... 3

System Integration ................................................ 3

ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 9

Real Time Clock ................................................... 9

Watchdog Timer ................................................ 10

Timers ............................................................. 10

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Ports ...................... 10

2-Wire Interface ................................................. 11

UART Ports ...................................................... 11

General-Purpose Ports ......................................... 11

Parallel Peripheral Interface ................................... 12

Controller Area Network (CAN) Interface ................ 13

Dynamic Power Management ................................ 13

Voltage Regulation .............................................. 14

Booting Modes ................................................... 16

Instruction Set Description ................................... 16

Development Tools ............................................. 17

Designing an Emulator Compatible Processor Board ... 18

Pin Descriptions .................................................... 19

Specifications ........................................................ 23

REVISION HISTORY

05/07—Revision PrE to Rev.0

Add new wording to Power Savings section

Revise driver types in Pin Descriptions

Line changes in footnotes for Specifications and Operating

Conditions

Replace Rise and Fall Times graphs in Capacitive Loading

section

Reorder Ball Assignments

SPORT timing and External Late Frame Sync diagrams

changed.

Operating Conditions ........................................... 23

Electrical Characteristics ....................................... 24

Absolute Maximum Ratings ................................... 25

Package Information ............................................ 25

ESD Sensitivity ................................................... 25

Timing Specifications ........................................... 26

Clock and Reset Timing ..................................... 27

Asynchronous Memory Read Cycle Timing ............ 28

Asynchronous Memory Write Cycle Timing ........... 30

SDRAM Interface Timing .................................. 32

External Port Bus Request and Grant Cycle Timing .. 33

Parallel Peripheral Interface Timing ...................... 35

Serial Port Timing ............................................ 38

Serial Peripheral Interface Ports—Master Timing ..... 41

Serial Peripheral Interface Ports—Slave Timing ....... 42

General-Purpose Port Timing ............................. 43

Timer Cycle Timing .......................................... 44

JTAG Test And Emulation Port Timing ................. 45

Output Drive Currents ......................................... 46

Power Dissipation ............................................... 48

Test Conditions .................................................. 48

Thermal Characteristics ........................................ 51

316-Ball Mini-BGA Ball Assignments .......................... 52

Outline Dimensions ................................................ 55

Surface Mount Design .......................................... 56

Ordering Guide ..................................................... 56

Rev. 0 | Page 2 of 56 | May 2007

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