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ADSP-BF538F
(Rev.:Rev0)

Blackfin® Embedded Processor

Analog Devices

ADSP-BF538F Datasheet PDF : 56 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

ADSP-BF538/ADSP-BF538F

System Interrupt Controllers (SIC)

The system interrupt controllers (SIC0, SIC1) provide the map-

ping and routing of events from the many peripheral interrupt

sources to the prioritized general-purpose interrupt inputs of

the CEC. Although the ADSP-BF538/ADSP-BF538F processors

provide a default mapping, the user can alter the mappings and

priorities of interrupt events by writing the appropriate values

into the interrupt assignment registers (SIC_IARx).

Table 3 describes the inputs into the SICs and the default map-

pings into the CEC.

Table 3. System and Core Event Mapping

Event Source

PLL Wakeup Interrupt

DMA Controller 0 Error

DMA Controller 1 Error

PPI Error Interrupt

SPORT0 Error Interrupt

SPORT1 Error Interrupt

SPORT2 Error Interrupt

SPORT3 Error Interrupt

SPI0 Error Interrupt

SPI1 Error Interrupt

SPI2 Error Interrupt

UART0 Error Interrupt

UART1 Error Interrupt

UART2 Error Interrupt

CAN Error Interrupt

Real Time Clock Interrupts

DMA0 Interrupt (PPI)

DMA1 Interrupt (SPORT0 Rx)

DMA2 Interrupt (SPORT0 Tx)

DMA3 Interrupt (SPORT1 Rx)

DMA4 Interrupt (SPORT1 Tx)

DMA8 Interrupt (SPORT2 Rx)

DMA9 Interrupt (SPORT2 Tx)

DMA10 Interrupt (SPORT3 Rx)

DMA11 Interrupt (SPORT3 Tx)

DMA5 Interrupt (SPI0)

DMA14 Interrupt (SPI1)

DMA15 Interrupt (SPI2)

DMA6 Interrupt (UART0 Rx)

DMA7 Interrupt (UART0 Tx)

DMA16 Interrupt (UART1 Rx)

DMA17 Interrupt (UART1 Tx)

DMA18 Interrupt (UART2 Rx)

DMA19 Interrupt (UART2 Tx)

Core

Event Name

IVG7

IVG8

IVG9

IVG10

Table 3. System and Core Event Mapping (Continued)

Event Source

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

TWI1 Interrupt

CAN Receive Interrupt

CAN Transmit Interrupt

Port F GPIO Interrupts A and B

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

Core

Event Name

IVG11

IVG12

IVG13

Event Control

The ADSP-BF538/ADSP-BF538F processors provide the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 32 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may also be written to clear (cancel) latched events. This

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event, pre-

venting the processor from servicing the event even though

the event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general-purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

Each SIC allows further control of event processing by provid-

ing three 32-bit interrupt control and status registers. Each

interrupt events shown in Table 3 on Page 8.

Rev. 0 | Page 8 of 56 | May 2007

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