74ALVCH16600DGG 데이터 시트보기 (PDF) - Nexperia B.V. All rights reserved

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74ALVCH16600DGG

18-bit universal bus transceiver; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74ALVCH16600

18-bit universal bus transceiver; 3-state

3 Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

74ALVCH16600DGG −40 °C to +85 °C

Name

TSSOP56

Description

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

Version

SOT364-1

4 Functional diagram

3 A0

5 A1

6 A2

8 A3

9 A4

10 A5

12 A6

13 A7

14 A8

15 A9

16 A10

17 A11

19 A12

20 A13

21 A14

23 A15

24 A16

26 A17

1 OEAB

2 LEAB

55 CPAB

55 CEAB

Figure 1. Logic symbol

B0 54

B1 52

B2 51

B3 49

B4 48

B5 47

B6 45

B7 44

B8 43

B9 42

B10 41

B11 40

B12 38

B13 37

B14 36

B15 34

B16 33

B17 31

OEBA 27

LEBA 28

CPBA 30

CEBA 29

aaa-028028

VCC

OEAB 1

CEAB 56

CPAB 55

LEAB 2

OEBA 27

CEBA 29

CPBA 30

LEBA 28

A0 3

A1 5

A2 6

A3 8

A4 9

A5 10

A6 12

A7 13

A8 14

A9 15

A10 16

A11 17

A12 19

A13 20

A14 21

A15 23

A16 24

A17 26

EN1

G2

2C3

C3

G2

EN4

G5

5C6

C6

G5

3D 1 1

4 1 6D

Figure 2. IEC logic symbol

54 B0

52 B1

51 B2

49 B3

48 B4

47 B5

45 B6

44 B7

43 B8

42 B9

41 B10

40 B11

38 B12

37 B13

36 B14

34 B15

33 B16

31 B17

aaa-028029

Figure 3. Bus hold circuit

74ALVCH16600

Product data sheet

data input

to internal circuit

001aal733

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 15 January 2018

© Nexperia B.V. 2018. All rights reserved.

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