S-89210ACNC-1C0TFG_ 데이터 시트보기 (PDF) - Seiko Instruments Inc
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S-89210ACNC-1C0TFG_ Datasheet PDF : 20 Pages
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Rev.4.0_01
MINI ANALOG SERIES CMOS COMPARATOR
S-89210/89220 Series
Test Circuit
1. Power supply voltage rejection ratio, input offset voltage
VDD
−
+
VIN
VDD / 2
VOUT
• Power supply voltage rejection ratio (PSRR)
Input offset voltage (VIO)
The input offset voltage (VIO) is defined as VIN − VDD / 2 when
VOUT is changed by changing VIN to VDD / 2 level. The power
supply voltage rejection ratio (PSRR) can be calculated by
following expression, with the value of VIO measured at each
VDD.
Test conditions:
When VDD = 1.8 V: VDD = VDD1, VIO = VIO1
When VDD = 5.0 V: VDD = VDD2, VIO = VIO2
Figure 4
PSRR = 20 log
VDD1 − VDD2
VIO1 − VIO2
2. Common-mode input signal rejection ratio, common-mode input voltage range
VDD
• Common-mode input signal rejection ratio (CMRR)
The common-mode input signal rejection ratio (CMRR) can be
calculated by the following expression, with the offset voltage
(VIO) set as VIN1 − VIN2 after VOUT is changed by changing VIN1.
Test conditions:
−
+
VOUT
When VIN2 = VCMR Max.: VIN2 = VINH, VIO = VIO1
When VIN2 = VDD / 2: VIN2 = VINL, VIO = VIO2
VIN1
VIN2
CMRR = 20 log
VINH − VINL
VIO1 − VIO2
Figure 5
• Common-mode input voltage range (VCMR)
Varying VIN2, the range of VIN2 that satisfies the common-mode
input signal rejection ratio (CMRR) is the common-mode input
voltage range (VCMR).
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