DSA400 데이터 시트보기 (PDF) - Microchip Technology

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DSA400

Configurable Four Output, Low Jitter Clock Generator for Automotive

Microchip Technology 

4.4 LVCMOS

DSA400

50 Ω

27Ω

FIGURE 4-4:

Typical LVCMOS Termination Scheme.

The 27Ω Series resistor complements the output impedance of about 23Ω to 50Ω impedance to match the line 50Ω

characteristic impedance to prevent reflections from the driver back to the receiver.

TABLE 4-4: LVCMOS OUTPUTS

Parameter Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

VOH

0.9 x VDD

—

—

Output Logic High, I = ±6 mA

V

VOL

—

—

0.1 x VDD

Output Logic Low, I = ±6 mA

Output

tR

Transition Time

(Note 1)

tF

—

1.1

2.0

Rise Time, 20% to 80%, CL= 15 pF

ns

—

1.3

2.0

Fall Time, 20% to 80%, CL= 15 pF

Frequency

f0

—

Output Duty

Cycle

SYM

44

—

100

MHz —

—

55

%—

IO Supply

Current (Note 2)

IDDIO

—

11

14

mA Per Output at 125 MHz, CL = 15 pF

Period Jitter

JPER

—

3

—

psRMS

Integrated

Phase Noise

JPH

—

0.3

—

—

0.38

—

psRMS

—

1.7

2.0

Note 1: See the Output Waveform section for more information.

CLK(0:3) = 125 MHz

200 kHz to 20 MHz @ 125 MHz

100 kHz to 20 MHz @ 125 MHz

12 kHz to 20 MHz @125 MHz

2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.

 2020 Microchip Technology Inc.

DS20006356A-page 9

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