AT26DF081A-SU 데이터 시트보기 (PDF) - Unspecified

부품명

상세내역

제조사

AT26DF081A-SU

8-megabit 2.7-volt Minimum SPI Serial Flash Memory

Unspecified 

Figure 2-1. 8-SOIC Top View

CS 1

SO 2

WP 3

GND 4

8 VCC

7 HOLD

6 SCK

5 SI

3. Block Diagram

CONTROL AND

CS

PROTECTION LOGIC

SCK

SI

SO

INTERFACE

CONTROL

AND

LOGIC

Y-DECODER

WP

X-DECODER

I/O BUFFERS

AND LATCHES

SRAM

DATA BUFFER

Y-GATING

FLASH

MEMORY

ARRAY

4. Memory Array

To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four

levels of granularity including a full chip erase. In addition, the array has been divided into phys-

ical sectors of various sizes, of which each sector can be individually protected from program

and erase operations. The sizes of the physical sectors are optimized for both code and data

storage applications, allowing both code and data segments to reside in their own isolated

regions. Figure 4-1 on page 5 illustrates the breakdown of each erase level as well as the break-

down of each physical sector.

4 AT26DF081A

3600I–DFLASH–5/2013

Share Link: