AT90CAN128-UL 데이터 시트보기 (PDF) - Atmel Corporation

부품명

상세내역

제조사

AT90CAN128-UL

8-bit Microcontroller with 128K Bytes of ISP Flash and CAN Controller

Atmel Corporation 

AT90CAN128

Interrupt Response Time

Assembly Code Example

in r16, SREG

cli

sbi EECR, EEMWE

sbi EECR, EEWE

out SREG, r16

C Code Example

; store SREG value

; disable interrupts during timed sequence

; start EEPROM write

; restore SREG value (I-bit)

char cSREG;

cSREG = SREG;

/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG;

/* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be

executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed. During this four clock cycle period, the Program Counter is

pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

increased by four clock cycles. This increase comes in addition to the start-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack

Pointer is incremented by two, and the I-bit in SREG is set.

15

4250E–CAN–12/04

Share Link: