AT90CAN128-UL 데이터 시트보기 (PDF) - Atmel Corporation

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AT90CAN128-UL

8-bit Microcontroller with 128K Bytes of ISP Flash and CAN Controller

Atmel Corporation 

Figure 10. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(4096 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0060 - 0x00FF

0x0100

0x10FF

0x1100

External SRAM

(0 - 64K x 8)

SRAM Data Access Times

0xFFFF

This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clkCPU cycles as described in Figure

11.

Figure 11. On-chip Data SRAM Access Cycles

T1

T2

T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Address valid

18 AT90CAN128

Memory Access Instruction

Next Instruction

4250E–CAN–12/04

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