BR24A01A-WM(2009) 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24A01A-WM
(Rev.:2009)

High Reliability Series EEPROMs I2C BUS

ROHM Semiconductor 

BR24A□□-WM series

Technical Note

●FAST-MODE and STANDARD-MODE

FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.

100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the

maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V～5.5V , 400kHz, namely, action is

made in FASTMODE. (Action is made also in STANDARD-MODE.)

●Sync data input / output timing

SCL

SDA

((in入pu力t) )

SDA

(o(u出tp力ut))

tHD:STA

tBUF

tR

tF tHIGH

tSU:DAT tLOW

tPD

tHD:DAT

tDH

○Input read at the rise edge of SCL

○Data output in sync with the fall of SCL

Fig.1-(a) Sync data input / output timing

SCL

tSU:STA

SDA

tHD:STA

tSU:STO

START BIT

STOP BIT

Fig.1-(b) Start-stop bit timing

SCL

SDA

D0 ACK

Write data

(n-th address)

ｔW R

Stop condition

Start condition

Fig.1-(c) Write cycle timing

SCL

SDA

DATA(1)

D1 D0 ACK

WP

DATA(n)

ACK

ｔWR

スSトtッopプcコoンndデitiィoシn ョン

tSU：WP

ｔHD：WP

Fig.1-(d) WP timing at write execution

SCL

SDA

WP

DATA(1)

D1 D0 ACK

DATA(n)

tHIGH:WP

ACK

tWR

○At write execution, in the area from the D0 taken clock rise of the first

DATA(1), to tWR, set WP=“LOW”.

○By setting WP “HIGH” in the area, write can be cancelled.

When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of

address under access is not guaranteed, therefore write it once again.

Fig.1-(e) WP timing at write cancel

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© 2009 ROHM Co., Ltd. All rights reserved.

3/17

2009.08 - Rev.C

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