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BR24G04FJ-3A 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24G04FJ-3A Datasheet PDF : 36 Pages
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BR24G04-3A
Block Diagram
*A0 1
A1 2
A2 3
GND 4
4Kbit EEPROM array
Address
9bit
decoder
Word
address register
8bit
Data
register
8 Vcc
7 WP
START
Control circuit
STOP
ACK
High voltage
generating circuit
Power source
voltage detection
Figure 3. Block diagram
6 SCL
5 SDA
* A0=Don't use
Pin Configuration
A0 1
8 Vcc
A1 2
A2 3
BR24G04-3A
7 WP
6 SCL
GND 4
5 SDA
Pin Descriptions
Terminal
Name
A0
Input/
Output
Input
Function
Dont use*1
A1
Input
Slave address setting*2
A2
Input
Slave address setting*2
GND
SDA
SCL
-
Input/
output
Input
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
WP
Input
Write protect terminal
Vcc
-
Connect the power source.
*1 Pins not used as device address may be set to any of H,L, and Hi-Z.
*2 A1 and A2 are not allowed to use as open.
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© 2014 ROHM Co., Ltd. All rights reserved.
TSZ22111 15 001
5/33
TSZ02201-0R2R0G100560-1-2
11.Jun.2019 Rev.004

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