BR24T128FVJ-W 데이터 시트보기 (PDF) - ROHM Semiconductor
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BR24T128FVJ-W Datasheet PDF : 37 Pages
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BR24T128-W
AC Characteristics (Unless otherwise specified, Ta=-40℃ to +85℃, Vcc=1.6V to 5.5V)
Parameter
Limit
Symbol
Min
Typ
Max
Clock Frequency
fSCL
-
-
400
Data Clock High Period
tHIGH
0.6
-
-
Data Clock Low Period
SDA,SCL(INPUT) Rise Time (1)
SDA,SCL (INPUT)Fall Time (1)
SDA(OUTPUT)Fall Time (1)
tLOW
1.2
-
-
tR
-
-
1.0
tF1
-
-
1.0
tF2
-
-
0.3
Start Condition Hold Time
tHD:STA
0.6
-
-
Start Condition Setup Time
tSU:STA
0.6
-
-
Input Data Hold Time
tHD:DAT
0
-
-
Input Data Setup Time
tSU:DAT
100
-
-
Output Data Delay Time
tPD
0.1
-
0.9
Output Data Hold Time
tDH
0.1
-
-
Stop Condition Setup Time
tSU:STO
0.6
-
-
Bus Free Time
tBUF
1.2
-
-
Write Cycle Time
tWR
-
-
5
Noise Spike Width (SDA and SCL)
tI
-
-
0.1
WP Hold Time
tHD:WP
1.0
-
-
WP Setup Time
tSU:WP
0.1
-
-
WP High Period
tHIGH:WP
1.0
-
-
(1) Not 100% TESTED.
Condition Input Data Level: VIL=0.2×Vcc VIH=0.8×Vcc
Input Data Timing Reference Level: 0.3×Vcc/0.7×Vcc
Output Data Timing Reference Level: 0.3×Vcc/0.7×Vcc
Rise/Fall Time: ≦20ns
Datasheet
Unit
kHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
ms
µs
µs
µs
µs
Serial Input / Output Timing
tR
tF1
tHIGH
SCL
70%
SDA
((I入N力PU) T)
tHD:STA
70%
30%
tBUF
70%
70% 70%
30%
30%
tSU:DAT
tLOW
70%
tPD
70%
30%
70%
30%
tHD:DAT
70%
30%
tDH
SDA
(OUT(出PU力T) )
70%
30%
30%
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
70%
30%
tF2
Figure 2-(a). Serial Input / Output Timing
70%
DATA(1)
D1
D0 ACK
DATA(n)
ACK
70%
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Figure 2-(d). WP Timing at Write Execution
70%
70%
tSU:STA
tHD:STA
70%
30%
START CONDITION
70%
tSU:STO
30%
STOP CONDITION
Figure 2-(b). Start-Stop Bit Timing
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
70%
70%
ACK
70%
tWR
Figure 2-(e). WP Timing at Write Cancel
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION START CONDITION
Figure 2-(c). Write Cycle Timing
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TSZ02201-0R2R0G100130-1-2
31.May.2013 Rev.003
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