MAX823(1997) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX823 Datasheet PDF : 8 Pages
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5-Pin Microprocessor Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.5V for MAX82_L, VCC = +4.5V to +5.5V for MAX82_M, VCC = +3.15V to +3.6V for MAX82_T, VCC = +3V
to +3.6V for MAX82_S, VCC = +2.7V to +3.6V for MAX82_R, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VOH
MAX82_L/M, VCC = VRST max,
ISOURCE = 120µA
MAX82_T/S/R, VCC = VRST max,
ISOURCE = 30µA
VCC - 1.5
0.8VCC
RESET Output Voltage
MAX82_L/M, VCC = VRST min,
ISINK = 3.2mA
MAX82_T/S/R, VCC = VRST min,
ISINK = 1.2mA
VOL
TA = 0°C to +70°C, VCC = 1V,
VCC falling, ISINK = 50µA
0.4
V
0.3
0.3
TA = -40°C to +85°C, VCC = 1.2V,
VCC falling, VBATT = 0V, ISINK = 100µA
RESET Output Short-Circuit
Current (Note 2)
ISOURCE
VOH
MAX82_L/M, RESET = 0V, VCC = 5.5V
MAX82_T/S/R, RESET = 0V, VCC = 3.6V
VCC > 1.8V, ISOURCE = 150µA
RESET Output Voltage
MAX824L/M, MAX825L/M,
VCC = VRST max, ISINK = 3.2mA
VOL
MAX824T/S/R, MAX825T/S/R,
VCC = VRST max, ISINK = 1.2mA
VCC to RESET Delay
WATCHDOG INPUT (MAX823/MAX824)
VRST - VCC = 100mV
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold (Note 3)
WDI Input Current (Note 4)
tWD
tWDI VIL = 0.4V, VIH = 0.8VCC
VIL
VIH
VCC = 5V
WDI = VCC, time average
WDI = 0V, time average
MANUAL-RESET INPUT (MAX823/MAX825)
MR Input Threshold
VIL
VIH
MR Pulse Width
MR Noise Immunity (pulse width
with no reset)
MR to Reset Delay
MR Pull-Up Resistance (internal)
0.3
0.8VCC
800
µA
400
0.4
V
0.3
20
µs
1.12 1.60 2.40 sec
50
ns
0.7VCC
0.3VCC
V
120
160
µA
-20
-15
0.3VCC
1.0
V
0.7VCC
µs
100
ns
500
ns
35
52
75
kΩ
Note 1: Over-temperature limits are guaranteed by design and not production tested.
Note 2: The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a µP bidirectional reset pin.
Note 3: WDI is internally serviced within the watchdog period if WDI is left unconnected.
Note 4: The WDI input current is specified as the average input current when the WDI input is driven high or low. The WDI input is
designed to drive a three-stated-output device with a 10µA maximum leakage current and a maximum capacitive load of
200pF. This output device must be able to source and sink at least 200µA when active.
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