AD1803 데이터 시트보기 (PDF) - Analog Devices
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AD1803 Datasheet PDF : 32 Pages
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AD1803
REGISTER BANKS
Register addresses are based on the Intel AC '97 specification.
Because the AC '97 specification lacks sufficient vendor defined
register space to control all extended features of the AD1803,
some control registers must be accessed indirectly using register
banks. See the BNK1 and BNK0 bits in Register 0x5C for details.
REGISTER ACCESS RESTRICTIONS
Nearly all control registers can be read from or written to at any
time. Below is a list of restrictions that must be followed to ensure
proper operation of the AD1803:
• The clock frequency delivered to the AD1803 on XTALI
must be identified (via a write to the XTAL1 bit and
XTAL0 bit in Register 0x5C) before the codec is enabled
(via a write of 0 to Bits DPDN or APDN in Register 0x3E).
• During ADC calibration, codec sample rate (Register 0x40),
and ADC source and gain level must not be changed. Cali
bration is initiated each time the AD1803’s ADC is enabled
(see Bit APDN in Register 0x3E) and whenever a 1 is written
to Bit ADCAL in Register 0x5C. Completion of calibration
is determined by polling the ADCAL bit.
GENERAL-PURPOSE I/O PIN OPERATION
Refer to Registers 0x4C through 0x54 and Register 0x60 for
complete details (see Figure 13).
Table 8. Voice Features
Feature
Power Supply
Maximum Sampling Frequency
Differential Handset Output
Single-Ended Line Output
Output Full-Scale Range
Output Attenuation Steps
Input Line/MIC Mux
Input Full-Scale Range
Input 0 dB/20 dB Gain Block
PGA, 0 dB to 22.5 dB Range
Single-Ended Input
Differential Input
Input Resistance
AD1803
3 V to 5 V
16 kHz
No
Yes, 600 Ω load
2.2 V p-p
+12 dB to −34.5 dB
Yes
0.777 V rms, 2.2 V p-p
Yes
Yes
Yes
No
10 kΩ min varies with gain
(see Table 9)
Table 9. Input Resistance vs. Gain Setting
20 dB
PGA Gain (dB) Gain Block
PGA Gain (dB)
0.0 to 22.5
Disabled
0.0 to 22.5
0.0 to 22.5
Enabled
20.0 to 42.5
RIN (kΩ)
100
10
Rev. A | Page 14 of 32
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