AD1803 데이터 시트보기 (PDF) - Analog Devices

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AD1803

Modem/Telephony Codec

Analog Devices 

AD1803

Bit Name

GPDN

DSTA

ASTA

VSTA

GSTA

Description

GPIO Power-Down. Setting this bit affects the behavior of the AD1803 only when it is configured in an AC '97 mode (see Register

0x3C). This bit determines whether the logic levels received on the general-purpose input/output (GPIO) pins are reflected on the

bits in Slot 12 of the AC '97 link, and whether or not the states of bits in Slot 12 determine the logic levels to drive out of GPIO pins

that are configured as outputs. See Bit SPGBP in Register 0x5E for mapping. Contrary to the AC '97 specification, the setting of this bit

does not actually control the power-up/power-down state of the GPIO pins. AD1803 GPIO pins are powered up and perform the

functions they are assigned by programming Register 0x4C through Register 0x54 and Register 0x5E.

0 = Slot 12 output bits reflect logic levels received on GPIO pins. Slot 12 input bits determine logic bevels to drive out GPIO pins

configured as outputs.

1 = Slot 12 output bits all 0 (default). Slot 12 input bits are ignored.

DAC Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for DAC power-up/power-down status

changes initiated by writes to Bit DPDN in this register. Because the AD1803 responds to a write of Bit DPDN before it is possible to

read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no effect on AD1803

behavior.

ADC Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for ADC power-up/power-down status

changes initiated by writes to Bit APDN in this register. Because the AD1803 responds to a write of Bit APDN prior to it being possible

to read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no effect on

AD1803 behavior.

Voltage Reference Status. This bit can be polled to monitor the status of the codec voltage reference of the AD1803. When read as a

0, the voltage reference is powered down or in the process of powering up. When read as a 1, the voltage reference is powered up or

in the process of powering down. Approximately 48 ms after Bit VPDN in this register is set to a 0, this bit transitions from a 0 to a 1

indicating that the voltage reference is fully powered up. Approximately 0.8 ms after VPDN is set to a 1, this bit transitions from a 1 to

a 0 indicating that the voltage reference is fully powered-down. If a clock is driven onto the XTALI pin (rather than generated by a

crystal placed between the XTALI pin and XTALO pin), and it is desired to stop this clock for additional system power savings, stop the

clock after this bit falls to 0. Writes to this bit have no effect on the behavior of the AD1803.

GPIO Status. This bit exists solely for AC '97 compatibility. Its purpose is to provide a handshake for DAC power-up/power-down

status changes initiated by writes to Bit GPDN in this register. However, since the AD1803 responds to a write of Bit GPDN prior to it

being possible to read this bit in a following serial interface frame, there is no reason to poll this status bit. Writes to this bit have no

effect on the behavior of the AD1803.

LINE DAC/ADC SAMPLE RATE CONTROL REGISTER

Address D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

0x40

SRG1 SRG0 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 0x3E80

This register is forced to its default only when power is first applied to the AD1803. Do not write to this register while an ADC calibration is in

progress (see Bit APDN in Register 0x3E and Bit ADCAL in Register 0x5C).

When the AD1803 serial interface is configured in DSP mode, writes to the lower byte of this register are temporarily placed in a holding

register and do not actually take effect until the upper byte is written. This ensures that the 16-bit sample rate only takes effect as a whole.

Reads of the lower byte of this register return the contents of this holding register that do not necessarily reflect the current sample rate.

Bit Name

SRG1,

SRG0

SR13 to

SR0

Description

Sample Rate Granularity. These bits select the LSB weighting of the Bits SR[13:0] (Sample Rate Select). These bits select a

fundamental LSB weighting of either 1 Hz, 8/7 Hz, or 10/7 Hz for Bits SR[13:0].

00 = SR[13:0] LSB weight is 1 Hz.

01 = SR[13:0] LSB weight is 8/7 Hz.

10 = SR[13:0] LSB weight is 10/7 Hz.

11 = Reserved.

Sample Rate Select. Bits SRG[1:0] (Sample Rate Granularity), these bits define the sample rate for both the ADC and DAC codec

channels. Permitted settings of SR[13:0] range from 6400 to 16000 when SRG[1:0] = 00, 5600 to 14,000 when SRG[1:0] = 01, and

4480 to 11,200 when SRG[1:0] = 10. The default sample rate is 16,000 Hz.

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