AD1803 데이터 시트보기 (PDF) - Analog Devices
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AD1803 Datasheet PDF : 32 Pages
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AD1803
TYPICAL SUPPLY CURRENT
Typical supply current is for most common modes of operation. All currents in mA, unless otherwise noted.
Table 2.
Resource
GPIO Weak Pull-Up Current per Pin
RESET is Asserted
XTALI Off (All Down)1
XTALI Enabled: Nominal Power
XTALI Enabled: Low Power
CLK_OUT Pin Running2
RESET is Deasserted and Analog and Digital Codec
in Full Power Mode
SPORT and CLK_OUT Active2, 3
XTALI in Low Power Mode2, 3
CLK_OUT Inactive (Low)3
VREF Powered Up3
ADC Enabled
DAC Enabled3, 5
ADC + DAC Enabled3, 5
ADC, DAC, + MON Enabled3, 4, 5
ADC, DAC, + MON Enabled3, 5, 6
3.3 V
~100
<30.0
1.4
1.0
1.6
2.6
2.2
1.7
1.9
7.3
8.2
9.2
9.3
10.2
5.0 V
~140 μA
<40.0 μA
2.4
1.7
3.2
6.4
5.7
4.3
4.5
12.4
13.7
14.7
14.9
16.3
Register Writes to Enter Mode
Default settings after power-on RESET
Default settings after power-on RESET
5C:R34P4 = 1
5C:R34P4 = 1, 64b1:XTLP = 1
5C:CLKEA = 1
Default settings after power-on RESET
64b1:XTLP = 1
5C:CLKED = 0
3E:VPDN = 0
3E:APDN = 0
3E:DPDN = 0
3E:APDN = DPDN = 0
3E:APDN = DPDN = 0, 5E:GPMON = 1
3E:APDN = DPDN = 0, 5E:GPMON = 1
1 Assumes all inputs are static (not switching) and all output loads are capacitive (nonresistive).
2 Excludes current drawn by CLK_OUT pin board loading.
3 Assumes the serial interface is configured in AC '97 primary mode with 20 pF loads on the SDATA_IN pin and BIT_CLK pin. Typical current is approximately 0.8 mA less if the
serial interface is configured in DSP mode with 20 pF loads on the SYNC pin, BIT_CLK pin, and SDATA_IN pin (due to a lower BIT_CLK frequency).
4 Assumes a 20 pF load on the G[4]/MOUT pin.
5 Assumes no DAC load, 0.6 mA should be added if a 600 Ω load is used.
6 Assumes the G[4]/MOUT pin is loaded with a 1 kΩ resistor in series with a parallel 4.7 kΩ resistor and 100 nF capacitor combination tied to digital ground. This filter, with the
output taken from the middle node, has a 1500 Hz corner to filter out high-frequency Σ-Δ noise. It generates an approximate 1 V p-p output when using a 5 V digital supply
with the monitor output configured as first order (Bit MMD1 and Bit MMD0 set to 10 in Register 0x60 Bank 2) if the filter output load is greater than or equal to 20 kΩ.
Rev. A | Page 5 of 32
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