AD1803 데이터 시트보기 (PDF) - Analog Devices

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AD1803

Modem/Telephony Codec

Analog Devices 

AD1803

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions

Mnemonic

Pin No. I/O

ANALOG SIGNALS

DVDD

3

I

DGND

2

I

AVDD

21

I

AGND

19

I

Rx

16

I

Tx

20

O

FILT

17

I

VREF

18

I

CLOCK SIGNALS

XTALI

5

I

XTALO

CLK_OUT

4

O

1

O

SERIAL INTERFACE SIGNALS1

RESET

10

I

BIT_CLK

SYNC

SDATA_IN

SDATA_OUT

6

I/O

9

I/O

7

O

8

I

CLK_OUT 1

24 G[5]

DGND 2

23 G[6]

DVDD 3

22 G[7]

XTALO 4

XTALI 5

BIT_CLK 6

AD1803

TOP VIEW

(Not to Scale)

21 AVDD

20 Tx

19 AGND

SDATA_IN 7

SDATA_OUT 8

18 VREF

17 FILT

SYNC 9

16 Rx

RESET 10

15 G[1]/MIC

G[4]/MOUT 11

14 G[0]

G[3]/WAKE 12

13 G[2]

Figure 9. Pin Configuration

Description

Digital Supply. Range: 5.0 V ± 10% or 3.3 V ± 10% (independent of AVDD).

Digital Ground. Must be at same potential as AGND.

Analog Supply. Range is 5.5 V through 3.0 V (independent of DVDD).

Analog Ground. Must be at same potential as DGND.

Receive (ADC) input.

Transmit (DAC) output.

ADC Filter Bypass. Requires 1 μF capacitor to AGND.

Voltage Reference. Requires 1 μF capacitor to AGND.

Crystal or Clock Input (12.288 MHz, 24.576 MHz, or 32.768 MHz). This clock input is neces­

sary only if the AD1803 is configured in either AC '97 primary or DSP mode, or if a wake

interrupt from an event is required (in any mode). This pin must be tied to DVDD or DGND

(not floated) when clock input is not necessary. If a crystal is used, it must be parallel

resonant first harmonic, and tied between this pin and the XTALO pin with load capacitance

specified by the crystal supplier. See the XTAL1 bit and the XTAL0 bit in Register 0x5C for

further details.

Crystal Output. This pin should be floated when a crystal is not used.

Buffered version of clock present on the XTALI pin, unless disabled. See the CLKED bit and

CLKEA bit in Register 0x5C for further details.

Active Low Power-Down. Level of power-down is determined by bits in Register 0x5C. This

pin must be asserted (driven low) as power is first applied until the supply is stable. The

AD1803 is RESET exclusively by an internal power-on RESET circuit.

Serial Data Clock. Output if the AD1803 configured in AC '97 primary or DSP mode. Input if

the AD1803 is configured in any AC '97 secondary mode.

Serial Data Frame Sync. Output if the AD1803 is configured in DSP mode. Input if the

AD1803 is configured in any AC '97 mode.

Serial Data Output from AD1803.

Serial Data Input to AD1803.

Rev. A | Page 9 of 32

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