LT1767EMS8 데이터 시트보기 (PDF) - Linear Technology

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LT1767EMS8

Monolithic 1.5A, 1.25MHz Step-Down Switching Regulators

Linear Technology 

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

APPLICATIONS INFORMATION

suitable, but the ESR should be <1Ω to ensure it can be

fully recharged during the off time of the switch. The

capacitor value is derived from worst-case conditions of

700ns on-time, 50mA boost current, and 0.7V discharge

ripple. This value is then guard banded by 2x for secondary

factors such as capacitor tolerance, ESR and temperature

effects. The boost capacitor value could be reduced under

less demanding conditions, but this will not improve

circuit operation or efficiency. Under low input voltage and

low load conditions, a higher value capacitor will reduce

discharge ripple and improve start up operation.

SHUTDOWN AND UNDERVOLTAGE LOCKOUT

Figure 4 shows how to add undervoltage lockout (UVLO)

to the LT1767. Typically, UVLO is used in situations where

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

load to the source and can cause the source to current limit

or latch low under low source voltage conditions. UVLO

prevents the regulator from operating at source voltages

where these problems might occur.

LT1767

VIN

IN

7µA

1.33V

R1

3µA

SHDN

C1 R2

GND

OUTPUT

VSW

VCC

+

1767 F04

Figure 4. Undervoltage Lockout

An internal comparator will force the part into shutdown

below the minimum VIN of 2.6V. This feature can be used

to prevent excessive discharge of battery-operated sys-

tems. If an adjustable UVLO threshold is required, the

shutdown pin can be used. The threshold voltage of the

shutdown pin comparator is 1.33V. A 3µA internal current

source defaults the open pin condition to be operating (see

Typical Performance Graphs). Current hysteresis is added

above the SHDN threshold. This can be used to set voltage

hysteresis of the UVLO using the following:

10

R1= VH − VL

7µA

( ) R2 =

1.33V

VH − 1.33V

+ 3µA

R1

VH – Turn-on threshold

VL – Turn-off threshold

Example: switching should not start until the input is

above 4.75V and is to stop if the input falls below 3.75V.

VH = 4.75V

VL = 3.75V

R1= 4.75V − 3.75V = 143k

7µA

( ) R2 =

1.33V

4.75V − 1.33V

= 49.4k

+ 3µA

143k

Keep the connections from the resistors to the SHDN pin

short and make sure that the interplane or surface capaci-

tance to the switching nodes are minimized. If high resis-

tor values are used, the SHDN pin should be bypassed with

a 1nF capacitor to prevent coupling problems from the

switch node.

SYNCHRONIZATION

The SYNC pin, is used to synchronize the internal oscilla-

tor to an external signal. The SYNC input must pass from

a logic level low, through the maximum synchronization

threshold with a duty cycle between 20% and 80%. The

input can be driven directly from a logic level output. The

synchronizing range is equal to initial operating frequency

up to 2MHz. This means that minimum practical sync

frequency is equal to the worst-case high self-oscillating

frequency (1.5MHz), not the typical operating frequency

of 1.25MHz. Caution should be used when synchronizing

above 1.6MHz because at higher sync frequencies the

amplitude of the internal slope compensation used to

sn1767 1767fas

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