EL7563CRE-T13 데이터 시트보기 (PDF) - Elantec -> Intersil

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EL7563CRE-T13

Monolithic 4 Amp DC:DC Step-down Regulator

Elantec -> Intersil 

EL7563C

Monolithic 4 Amp DC:DC Step-down Regulator

Pin Descriptions

Pin Number

1

2

3

4

5

6

7

8

9

Pin Name

VREF

SGND

COSC

VDD

VTJ

PGND

PGND

VIN

STP

10

STN

11

PGND

12

PGND

13

PGND

14

LX

15

LX

16

VHI

17

VDRV

18

PG

19

FB

20

EN

Pin Function

Bandgap reference bypass capacitor; typically 0.1µF to SGND

Control circuit negative supply or signal ground

Oscillator timing capacitor (see performance curves)

Control circuit positive supply; normally connected to VIN through an RC filter

Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Power supply input of the regulator; connected to the drain of the high-side NMOS power FET

Auxilliary supply tracking positive input; tied to regulator output to synchronize start up with a second supply; leave open for

stand alone operation; 2µA internal pull down current

Auxilliary supply tracking negative input; connect to output of a second supply to synchronize start up; leave open for stand

alone operation; 2µA internal pull up current

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Ground return of the regulator; connected to the source of the low-side synchronous NMOS power FET

Inductor drive pin; high current output whose average voltage equals the regulator output voltage

Inductor drive pin; high current output whose average voltage equals the regulator output voltage

Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF capacitor

Positive supply of low-side driver and input voltage for high side boot strap

Power good window comparator output; logic 1 when regulator output is within ±10% of target output voltage

Voltage feedback input; connected to external resistor divider between VOUT and SGND; a 125nA pull-up current forces

VOUT to SGND in the event that FB is floating

Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open; a capacitor can be added at

this pin to delay the start of converter

4

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