CXD1852Q 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD1852Q Datasheet PDF : 30 Pages
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CXD1852Q
2. Pin Description
Pin No. Symbol
I/O
Description
VDD
+3.3V power supply
VSS
Connect to ground.
2
XTL0O
3
XTL0I
O Video decoder master clock. Input the clock to XTL0I or connect an
oscillator between XTL0I and XTL0O. The recommended frequencies are
I 27MHz, 28.6363MHz (NTSC 8fsc) and 35.4686MHz (PAL 8fsc).
5, 6, 119,
120
HA0 to HA3
I
When the host interface operates in parallel mode, these pins are the
register address inputs. In serial mode, HA0 is the serial data input, and
HA1 to HA3 should be fixed to low level.
7 to 13,
16
HD0 to HD7
I/O
When the host interface operates in parallel mode, these pins are the
register data I/Os. In serial mode, HD0 is the serial data output, and HD1
to HD7 should be fixed to low level.
17 to 21,
23, 24, MA0 to MA8 O
32, 33
DRAM address signal outputs. Connect to the DRAM address pins so that
the numbers match.
34 XRAS
O Row address strobe signal output. Connect to the DRAM RAS signal pin.
35 XMWE
O DRAM write enable signal output. Connect to the DRAM WE signal pin.
36
XCAS2/
MA9
Used when connecting 8 Mbits of DRAM. Connect to the upper word
(256K to 512K-1) DRAM CAS signal pin (for both the upper and lower
O bytes) when the DRAM configuration is 256 Kwords × 16 bits × 2, and to
the MA9 pin (for two DRAMs) when the DRAM configuration is 512 Kwords
× 8 bits × 2.
37 XCAS0
DRAM column address strobe signal output. Connect to the lower word
O
(0 to 256K-1) DRAM CAS signal pin (for both the upper and lower bytes)
when the DRAM configuration is 256Kwords × 16 bits × 2, and to all
DRAM CAS signal pins in all other cases.
38 to 43, MD0 to
46 to 55 MD15
I/O
DRAM data signal I/Os. Connect to the DRAM data pins so that the
numbers match.
56 OSDEN
I
OSD enable signal. The enabled polarity is changed by the register
settings.
OSDB,
57 to 59 OSDG,
OSDR
OSD data inputs. When the signal input to the OSDEN pin is enabled, the
I color registered in the color table which is specified by these three inputs
(3 bits) is output as the image data.
62 XVOE
Video output enable signal. Image data output and DCLK output are
I
enabled when this pin is low, and disabled when this pin is high (high
impedance). Note that the output control register must be set to output
enable for output to be enabled.
63 to 70
R/Cr0 to
R/Cr7
71 to 73, G/Y0 to
76 to 88 G/Y7
81 to 88
B/Cb0 to
B/Cb7
Image data outputs. The output data format (RGB, YCbCr, etc.) and the
O correspondence between the pins and output data can be changed by
setting the registers.
89 DCLK
Dot clock (DCLK) signal. The DCLK frequency is normally 13.5MHz.
I/O DCLK can be input from this pin, or frequency divided from the clock input
and output from this pin.
–3–
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