CS5106LSW24 데이터 시트보기 (PDF) - Cherry semiconductor
부품명
상세내역
제조사
CS5106LSW24 Datasheet PDF : 12 Pages
| |||
Theory of Application: continued
The equivalent down slope at the current sense resistor for
this application circuit is:
( ) Slope @ R12 = Inductor_Slope ´
NST2
NPT2
´
NPT3
NST3
´ R12
V
µs
After choosing R9 and C9 to generate a ramp with a time
constant of about 5 times the oscillator period, R10 and R11
can be chosen for the voltage at RAMP2 to be 1.75 of the
voltage across R12.
Synchronous Rectification
Synchronous rectification was chosen to reduce losses in
the forward converter. Improvements in efficiency will be
most significant in low voltage, medium and high current
converters where improvement in conduction loss offsets
any added losses for gate drive.
In the application circuit Q4 is turned on and off by the for-
ward transformer. Q5 is turned on and off through pulse
transformer T4 and the gate driver formed by Q6 and Q7.
Because Q4 and Q5 are driven through different types of
components, differences in propagation delay must be con-
sidered. The DLYSET resistor should be chosen to avoid
shoot-through or excessive off time.
Gate Drive Capability
All GATE drive outputs have nominal peak currents of
0.5A. See Figures 6 and 7 for typical rise and fall times.
70
60
50
Rise Time
40
70
60
50
Rise Time
40
Fall Time
30
20
10
0
50
200
500
1000
1500
Load Capacitance (pF)
2000
Figure 7: Typical GATE1 switching times.
Design Considerations
The circuit board should utilize high frequency layout
techniques to avoid pulse width jitter and false triggering
of high impedance inputs. Ground plane(s) should be
employed. Signal grounds and power grounds should be
run separately. Portions of the circuit with high slew rates
or current pulses should be segregated from sensitive
areas. Shields and decoupling capacitors should be used as
required.
Special care should be taken to prevent coupling between
the SYNC leads and the surrounding leads. Depending on
the circuit board layout and component values, decoupling
capacitors or reduction in resistor values might be required
to reduce noise pick-up on the FADJ and DLYSET resistors.
Decoupling capacitors or active pull-up/down might be
required to prevent false triggering of the ENABLE and
PROGRAM leads.
30
20
Fall Time
10
0
50
100
200
500
1000
Load Capacitance (pF)
2000
Figure 6: Typical GATE2, 2B switching times.
11
Share Link: 