CS5106LSW24 데이터 시트보기 (PDF) - Cherry semiconductor
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CS5106LSW24 Datasheet PDF : 12 Pages
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Electrical Characteristics: TJ = -40¡C to 125¡C, VSS = 9 to 16V, V5REF ILOAD = 2mA, SYNCOUT Free Running, unless other-
wise specified. For All Specs: UVSD=6V, OVSD = 0V, ENABLE = 0V, ILIM(1,2) = 0,VFB(1,2) = 3V,RFADJ = RDLYSET = 27.4k½.
PARAMETER
TEST CONDITIONS
s GATE 2, 2B Non-Overlap Delay
GATE2 Turn-on Delay
from GATE2B
Measure delay from GATE2B going low
@1.7V to GATE2 going high @1.7V.
GATE2B Turn-on Delay
from GATE2
Measure delay from GATE2 going low
@1.7V to GATE2B going high @1.7V.
MIN
20.0
20.0
TYP
45.0
45.0
MAX UNIT
70.0
ns
70.0
ns
s GATE 1, 2, 2B Rise & Fall Times
GATE1 Rise Time
GATE1 Fall Time
GATE2 Rise Time
GATE2 Fall Time
GATE2B Rise Time
GATE2B Fall Time
VSS=12V,VCC=VSS-VDON
Measure GATE1 Rise Time from
90% to 10%. CLOAD = 150pF.
Measure GATE1 Fall Time from
10% to 90%. CLOAD = 150pF.
Measure GATE2 Rise Time from
90% to10%. CLOAD = 50pF.
Measure GATE2 Fall Time from
10% to 90%. CLOAD = 50pF.
Measure GATE2B Rise Time from
90% to10%. CLOAD = 50pF.
Measure GATE2B Fall Time from
10% to 90%. CLOAD = 50pF.
50.0
80.0
ns
30.0
60.0
ns
50.0
80.0
ns
15.0
30.0
ns
50.0
80.0
ns
15.0
30.0
ns
PACKAGE LEAD #
1
LEAD SYMBOL
UVSD
2
OVSD
3
V5REF
4
OAM
5
OAOUT
6
OUVDELAY
7
ILIM1
8
RAMP1
Package Lead Description
FUNCTION
Undervoltage shutdown lead. Typically this lead is connected through a
resistor divider to the main high voltage (VIN) line. If the voltage on this lead
is less than 5V then a fault is initiated such that GATE1, GATE2 and GATE2B
go low.
Overvoltage shutdown lead. Typically this lead is connected through a resistor
divider to the main high voltage (VIN) line. If the voltage on this lead exceeds
5V then a fault is initiated such that GATE1, GATE2 and GATE2B go low.
5V reference output lead. Capable of 20mA nominal output. If this lead falls
to 4.5V, a fault is initiated such that GATE1, GATE2 and GATE2B go low.
Auxiliary error amplifier minus input. This lead is compared to 1.2V nominal
on the auxiliary error amp plus lead and represents the VSS voltage divided
by ten.
Auxiliary error amplifier output lead. Source current 300µA max.
Output undervoltage timing capacitor lead. If the controlled output voltages
of either the main or the auxiliary supply are such that either VFB1 or VFB2 is
greater that 4.1V nominal, then capacitor from OUVDELAY to ground will
begin charging. If the over voltage duration is such that the OUVDELAY
voltage exceeds 5V, then a fault will be initiated such that GATE1, GATE2
and GATE2B will go low.
Pulse by pulse over current protection lead for the auxiliary PWM. A voltage
exceeding 1.2V nominal on ILIM1 will cause GATE1 to go low. A voltage
exceeding 1.4V nominal on ILIM1 will cause GATE1 to go low for at least two
clock cycles.
Current Ramp Input Lead for the Auxiliary PWM. A voltage which is linear
with respect to current in the primary side of the auxiliary trans former is
usually represented on this lead. A voltage exceeding VFB1 - 0.13 on RAMP1
will cause GATE1 to go low.
6
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