SC1402(2001) 데이터 시트보기 (PDF) - Semtech Corporation

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SC1402
(Rev.:2001)

Multi-Output, Low-Noise Power Supply Controller for Notebook Computers

Semtech Corporation 

SC1402

POWER MANAGEMENT

Current Sense (CSH,CSL)

The output current of the power supply is sensed as the volt-

age drop across an external resistor between the CSH and

CSL pins. Over-current is detected when the current sense

voltage exceeds +/-100mV. The negative current limit (i.e. -

100mV) is required for operation with PSAVE mode disabled,

and also to limit the output current when charging the bulk

supply capacitor of the 12V regulator. A positive over-current

will turn off the high-side driver, a negative over-current will turn

off the low-side driver, each on a cycle by cycle basis. The

current sense is also used for peak current feed back in the

main PWM loop and for determining the current level for enter-

ing power save mode and the turn off time for the synchronous

rectifier.

Oscillator

The SC1402 oscillator frequency is trimmed to +/- 10%. When

the SYNC pin is set high the oscillator runs at 300kHz; when

SYNC is set low the frequency is 200kHz. The oscillator can

also be synchronized to the falling edge of a clock on the SYNC

pin with a frequency between 240kHz and 350kHz. In general,

200kHz operation is used for highest efficiency, and the 300kHz

for minimum output ripple and/or smaller inductor and output

capacitor sizes.

Fault Protection

In addition to cycle-by-cycle current limit, the SC1402 moni-

tors over-temperature, and output over-voltage and under-volt-

age conditions. The over-temperature detect will shut the part

down if the die temperature exceeds 150°C with 10°C of hys-

teresis.

If either SMPS output is greater than 7% above its nominal

value, both SMPS are latched off and synchronous rectifiers

are latched on. To prevent the output from ringing below, ground

a 1A Schottky diode should be placed across each output,

anode at GND.

Two different levels of undervoltage are detected. If the output

falls 5% below its nominal output, the RESET output is pulled

low. If the output falls 30% below its nominal output following a

start-up delay, both SMPS are latched off.

Both of the latched fault modes will remain in effect until SHDN

or RUN/ON3 is toggled or the V+ input is brought below 1V.

Shutdown and Operating Modes

Holding the SHDN pin low disables the SC1402, reducing the

V+ input current to <10uA. When SHDN goes high, the part

enters a standby mode where the VL regulator and VREF are

enabled. Turning on either SMPS will put the SC1402 in run

mode.

SHDN RUN/ TIME/ MODE DESCRIPTION

ON3 ON5

Low

X

X

Shut- Minimum bias

down

current

High

Low

Low Standby VREF and VL

regulator

enable

High High High

Run

Mode

Both SMPS

Running

Output Voltage Selection

If FB is connected to ground, internal resistors setup 3.3V and

5V output voltages. If external resistors are used, the internal

feedback is disabled and the output is regulated based on 2.5V

at the FB pin.

12OUT Supply

The 12OUT linear regulator is capable of supplying 120mA.

The input voltage to the 12OUT regulator is generated by a

secondary winding on the 5V SMPS inductor.

A heavy load on the 12OUT regulator when the 5V SMPS is in

PSAVE will cause the VDD input to drop, browning out the

regulator. If the output drops 0.8% from its nominal value, the

5V SMPS is forced out of PSAVE mode and into continuous

conduction mode for 8 cycles. This recharges the bulk input

capacitor on VDD. The 12OUT linear regulator has a current

limit to prevent damage under short circuit conditions.

Over-voltage protection is provided on the VDD input. If the

VDD input is above 19V, an over-voltage is detected and a

10mA current shunt load is applied to VDD. The over-voltage

threshold has 0.5V of hysteresis.

Power up Controls and Soft Start

The user has control of the SC1402 startup sequence by set-

ting the SEQ, RUN/ON3 and TIME/ON5 pins as described in

the following table.

Each SMPS contains its own counter and DAC to gradually

increase the current limit at startup to prevent input surge cur-

rents. The current limit is increased from 0, 20%, 40%, 60%,

80%, to 100% linearly over the course of 512 switching cycles.

A RESET output is also generated at startup. The

RESET pin is held low for 32K switching cycles. Another timer

is used to enable the undervoltage protection. The undervoltage

protection circuitry is enabled after 6144 switching cycles at

which time the SMPS should be in regulation.

When SEQ is set to REF, the RESET only monitors the 3.3V

SMPS in regulation. The 5V SMPS is ignored.

 2001 Semtech Corp.

11

www.semtech.com

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