T8531A-TL-DB 데이터 시트보기 (PDF) - Agere -> LSI Corporation

부품명

상세내역

제조사

T8531A-TL-DB

Multichannel Programmable Codec Chip Set

Agere -> LSI Corporation 

Preliminary Data Sheet

September 2001

T8531A/T8532 Multichannel Programmable

Codec Chip Set

General Description (continued)

T8531A Description

As shown in Figure 4, the T8531A contains a digital signal processor (DSP) engine surrounded by a customized

input/output (I/O) frame. The I/O frame performs the µ-law or A-law conversion as well as the decimation and inter-

polation functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The

sigma-delta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s.

A key function of the I/O frame is to control the timing of the digital data going to the signal processor so that group

delay is minimized.

The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for

the chip set.

The microcontroller interface is used to run the ROM routines and to download the gain, filter, and balance network

settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the

T8532 octal chips.

JTAG

HDS

PLL

CLOCK

SYNTHESIZER

SYSTEM PCM INTERFACE

DATA TRANSFER

µ/A-LAW CONVERTER

DIGITAL

SIGNAL

PROCESSING

ENGINE

DSP

ROM

DSP

RAM

MICRO-

PROCESSOR

CONTROL

INTERFACE

TSA

DECIMATOR

INTERPOLATOR

T8532 OVERSAMPLED INTERFACE

T8532 CONTROL INTERFACE

OSDX/R[3:0]

Figure 4. T8531A Block Diagram

UPCS

UPCK

UPDI

UPDO

HIGHZB

RSTB

T_SYNC

TSTCLK

TEST

VDD

VSS

0505(F)

Agere Systems Inc.

5

Share Link: