DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

MSM7731-01 데이터 시트보기 (PDF) - Oki Electric Industry

부품명
상세내역
제조사
MSM7731-01
OKI
Oki Electric Industry OKI
MSM7731-01 Datasheet PDF : 43 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
¡ Semiconductor
MSM7731-01
LGC/AGC
This pin turns ON or OFF the gain control function to control the input level and prevent
howling by means of gain controls (GainL/A) provided in the RinL/A inputs of the echo
canceler. The gain controller adjusts the RIN input level when it is –10 dBm0 or above, and it
has the control range of 0 to –8.5 dB. A logic "0" turns the function ON and a logic "1" turns the
function OFF. Since this pin is ORed with the CR4-B0 and CR5-B0 bits of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.
Notes:
Lxx/Axx: In the above, Lxx refers to line echo canceler control pins and Axx to acoustic echo
canceler control pins.
xxL/xxA: In the above pin descriptions, xxL refers to line echo canceler functions and xxA to
acoustic echo canceler functions.
GLPADTHR
This is the mode control pin for the attenuators (LPADL/A) provided in the SinL/A inputs and
the amplifiers (GPADL/A) provided in the SoutL/A outputs of the echo canceler. A logic "0"
selects the "through mode" and a logic "1" selects the normal mode (PAD operation). The levels
are set by the CR10 register. Settings of ±18, ±12, ±6 and 0 dB are possible. The default setting
is ±12 dB. If the echo return loss (value of returned echo) is amplified, set the LPAD level such
that echo return loss will be attenuated. It is recommended to set the GPAD level to the positive
level equal to the LPAD level. Since this pin is ORed with the CR1-B2 bit of the control register,
set the pin to a logic "0" when controlling by the control register. Because data is shifted into this
pin in synchronization with the rising edge of the SYNC signal, hold the data at the pin for 250
ms or longer. For further details, refer to the electrical characteristics.
NCTHR
This is the noise canceler "through mode" control pin. In the "through mode" the noise canceler
is halted and data is directly output. A logic "0" selects the normal mode (noise canceler
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B0
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics. When this pin is changed from normal mode to "through mode", approximately
20 ms of data dropout will occur.
SLPTHR
This is the "through mode" control pin for the transmit slope filter. In the "through mode", the
filter is halted and data is directly output. A logic "0" selects the normal mode (slope filter
operation) and a logic "1" selects the "through mode". Since this pin is ORed with the CR1-B1
bit of the control register, set the pin to a logic "0" when controlling by the control register.
Because data is shifted into this pin in synchronization with the rising edge of the SYNC signal,
hold the data at the pin for 250 ms or longer. For further details, refer to the electrical
characteristics.
11/43

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]