DS1991L 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1991L Datasheet PDF : 14 Pages
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DS1991
BLOCK SELECTOR CODES OF THE DS1991 Figure 6
Block Nr. Address Range LS Byte
Codes
MS Byte
0 to 7
00 to 3FH
56 56 7F 51 57 5D 5A 7F
0
identifier
9A 9A B3 9D 64 6E 69 4C
1
password
9A 9A 4C 62 9B 91 69 4C
2
10H to 17H
9A 65 B3 62 9B 6E 96 4C
3
18H to 1FH
6A 6A 43 6D 6B 61 66 43
4
20H to 27H
95 95 BC 92 94 9E 99 BC
5
28H to 2FH
65 9A 4C 9D 64 91 69 B3
6
30H to 37H
65 65 B3 9D 64 6E 96 B3
7
38H to 3FH
65 65 4C 62 9B 91 96 B3
Write SubKey [99H]
The Write Subkey command is used to enter data into the selected subkey. Since the subkeys are secure,
the correct password is required to access them. The sequence begins by reading the ID field; the
password is then written back. If the password is incorrect, the transaction is terminated. Otherwise, the
data following is written into the secure area. The starting address for the write sequence is specified in
the command word. Data can be continuously written until the end of the secure subkey is reached or
until the DS1991 is reset. The command sequence is shown in Figure 5, 2nd page, center column.
Read SubKey [66H]
The Read Subkey command is used to retrieve data from the selected subkey. Since the subkeys are
secure, the correct password is required to access them. The sequence begins by reading the ID field; the
password is then written back. If the password is incorrect, the DS1991 will transmit random data.
Otherwise the data can be read from the subkey. The starting address is specified in the command. Data
can be continuously read until the end of the subkey is reached or until the DS1991 is reset. The
command sequence is shown in Figure 5, 2nd page, left column.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances, the
DS1991 is a slave device. The bus master is typically a micro-controller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specified time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1- bus has only a single line by definition; it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have an open
drain connections or 3-state outputs. The DS1991 is an open drain part with an internal circuit equivalent
to that shown in Figure 7. The bus master can be the same equivalent circuit. If a bidirectional pin is not
available, separate output and input pins can be tied together.
The bus master requires a pullup resistor at the master end of the bus, with the bus master circuit
equivalent to the one shown in Figures 8a and 8b. The value of the pullup resistor should be
approximately 5 kΩ for short line lengths.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum
data rate of 16.3k bits per second. The idle state for the 1-Wire bus is high. If, for any reason a transaction
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