AK4541VQ 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AK4541VQ

AC’97™ Rev 2.1 Multimedia Audio CODEC

Asahi Kasei Microdevices 

[ASAHI KASEI]

[AK4541]

n Power On

Note that a AK4541 must be in cold reset at power on and RESET# must be low until master clock becomes stable,

or a reset must be done once master clock is stable. AVdd or DVdd can be powered from independent supplies.

Vdd

RESET#

SDATA_OUT=”L”

SYNC=”L”

BIT_CLK

Initialize Registers

start up crystal oscillation

Trst2clk

When using the AK4541 in the multiple codec mode, all codec’s connected to the AC-link are waken up at the same

time. A common reset line should be used to insure clock synchronization after power up.

nCold Reset Timing

Note that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for a cold reset to occur.

The AK4541 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each

analog output is in Hi-Z state except for PC Beep while RESET# pin is low. The PC Beep is directly routed to L

& R line outputs when AK4541 is in Cold Reset. This is done to allow system sounds to be passed to speaker

removing for an internal redundant speaker.

At the rising edge of RESET#, the AK4541 initiates the initialization of analog circuit , which takes 516fs cycles.

After that, the mixer of the AK4541 is ready for normal operation.

Status bit in the slot 0 is “0” (not ready) when the AK4541 is in RESET period ( “L”) or in initialization process.

After initialization cycles, the status bit goes to “1” indicating a ready condition.

Trst_low

Trst2clk

RESET#

VIL

SDATA_OUT=”L”

SYNC=”L”

BIT_CLK

When the AK4541 is used under the multiple codec configuration and when cold reset is issued, all AK4541

connected to the AC-link will execute a cold reset concurrently.

nWarm Reset

The AK4541 initiates a warm reset process by receiving a single pulse on the sync(Pin10). The AK4541 then clears

PR4 bit and PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0 ∼PR3 or

PR6,7 bits in Powerdown Control Register(26h). Note that SYNC signal should synchronize with BIT_CLK after

AK4541 starts to output BIT_CLK clock. And if an external clock is used, an external clock should be supplied

before issuing a sync pulse for warm reset.

Tsync_high

Tsync2clk

SYNC

VIH

BIT_CLK

<M0047-E-01>

-8-

1999/01

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