AD9742 데이터 시트보기 (PDF) - Analog Devices
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AD9742 Datasheet PDF : 32 Pages
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Data Sheet
AD9742
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
(MSB) DB11 1
28 CLOCK
DB10 2
27 DVDD
DB9 3
26 DCOM
DB8 4
25 MODE
DB7 5
24 AVDD
DB6 6 AD9742 23 RESERVED
TOP VIEW
DB5 7 (Not to Scale) 22 IOUTA
DB4 8
21 IOUTB
DB3 9
20 ACOM
DB2 10
19 NC
DB1 11
18 FS ADJ
(LSB) DB0 12
17 REFIO
NC 13
16 REFLO
NC 14
15 SLEEP
NC = NO CONNECT
Figure 3. 28-Lead SOIC and 28-Lead TSSOP Pin Configuration
DB5 1
DB4 2
DVDD 3
DB3 4
DB2 5
DB1 6
(LSB) DB0 7
NC 8
PIN 1
INDICATOR
AD9742
TOP VIEW
(Not to Scale)
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 ACOM
18 AVDD
17 AVDD
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER
GROUND PLANE FOR ENHANCED ELECTRICAL
AND THERMAL PERFORMANCE.
Figure 4. 32-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions (N/A = Not Applicable)
SOIC/TSSOP LFCSP
Pin No.
Pin No.
Mnemonic Description
1
27
DB11
Most Significant Data Bit (MSB).
2 to 11
28 to 32, DB10 to DB1 Data Bits 10 to 1.
1, 2, 4 to 6
12
7
DB0
Least Significant Data Bit (LSB).
13, 14
8, 9
NC
No Internal Connection.
15
25
SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16
N/A
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
17
23
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (that is, tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (that is, tie
REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated.
18
24
FS ADJ
Full-Scale Current Output Adjust.
19
N/A
NC
No Internal Connection.
20
19, 22
ACOM
Analog Common.
21
20
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
21
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
N/A
RESERVED Reserved. Do not connect to common or supply.
24
17, 18
AVDD
Analog Supply Voltage (3.3 V).
25
16
MODE
Selects Input Data Format. Connect to DCOM for straight binary, DVDD for twos complement.
N/A
15
CMODE
Clock Mode Selection. Connect to CLKCOM for single-ended clock receiver (drive CLK+ and float
CLK–). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations on-chip).
26
10, 26
DCOM
Digital Common.
27
3
DVDD
Digital Supply Voltage (3.3 V).
28
N/A
CLOCK
Clock Input. Data latched on positive edge of clock.
N/A
12
CLK+
Differential Clock Input.
N/A
13
CLK−
Differential Clock Input.
N/A
11
CLKVDD
Clock Supply Voltage (3.3 V).
N/A
14
CLKCOM
Clock Common.
N/A
EPAD
It is recommended that the exposed pad be thermally connected to a copper ground plane for
enhanced electric and thermal performance.
Rev. C | Page 7 of 32
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