ICS650R-07(V2) 데이터 시트보기 (PDF) - Integrated Circuit Systems

부품명

상세내역

제조사

ICS650R-07
(Rev.:V2)

Broadcom Clock Source

Integrated Circuit Systems 

ICS650-07B

Broadcom Clock Source

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Referenced to GND

Ambient Operating Temperature

Soldering Temperature

Max of 20 seconds

Storage temperature

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

Input High Voltage, VIH, X1 pin only

Input Low Voltage, VIL, X1 pin only

Input High Voltage, VIH, PS pin only

Input Low Voltage, VIL, PS pin only

Output High Voltage, VOH

IOH=-12 mA

Output Low Voltage, VOL

IOL=12 mA

Output High Voltage, VOH, CMOS level

IOH=-4 mA

Operating Supply Current, IDD

No Load

Short Circuit Current

Each output

Internal pull-up resistor

PS, OE

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

Input Frequency

Output Clock Rise Time

0.8 to 2.0 V

Output Clock Fall Time

2.0 to 0.8 V

Output Clock Duty Cycle

At VDD/2

Frequency error

All clocks

Absolute Jitter, short term

Variation from mean

Minimum Typical Maximum Units

7

V

-0.5

VDD+0.5 V

0

70

°C

260

°C

-65

150

°C

3

5.5

V

VDD/2 + 1 VDD/2

V

VDD/2 VDD/2 - 1 V

VDD-0.5

V

0.5

V

2.4

V

0.4

V

VDD-0.4

V

35

mA

±50

mA

200

kΩ

25.000

MHz

1.5

ns

1.5

ns

40

50

60

%

0

ppm

±200

ps

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The ICS650-07B requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between each VDD and GND, as close to the ICS650-07B as

possible. A series termination resistor of 33 Ω may be used for each clock output. The 25.00 MHz crystal

must be connected as close to the chip as possible. The crystal should be a fundamental mode (do not use

third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to ground and X2

to ground to optimize the initial accuracy. The value of these capacitors is given by the following equation,

where CL is the crystal load capacitance: Crystal caps (pF) = (CL-6) x 2. So for a crystal with 16 pF load

capacitance, two 20 pF caps should be used.

MD S 650-07B A

3

Revision 042600

Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

Share Link: