SC9256S 데이터 시트보기 (PDF) - Silan Microelectronics

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SC9256S

PLL FOR DTS

Silan Microelectronics 

Silan

Semiconductors

LSB

Address D3H

PE1 PE2 PE3

SC9256

MSB

PE1 PE2 PE3

000

001

010

011

100

101

110

111

PHASE ERROR (PE)

f ­ PE< 0.55 s

f ­ ‚ f ­ 0.55 s PE< 1.65 s

f ­ ‚ f ­ 1.65 s PE< 2.75 s

f ­ ‚ f ­ 2.75 s PE< 3.85 s

f ­ ‚ f ­ 3.85 s PE< 4.95 s

f ­ ‚ f ­ 4.95 s PE< 6.05 s

f ­ ‚ f ­ 6.05 s PE< 7.15 s

f ­ ‚ 7.15 s PE

The phase error data can be read from the output register (D3H) as serial data PE1~PE3.

Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change

with a phase error greater than ±6.05µs.

Frequency change

WAIT

Phase error detection

start Reset bit 1

WAIT

Time interval exceeding that of

reference frequcncy cycle

ENABLE=1?

YES

UNLOCK bit =0?

NO

NO (UNLOCK)

YES (Lock)

Check phase error

detection bits

PE1,PE2 and PE3

NO PE1=1,PE2=0,PE3=1?

YES

f ­ Phase error=greater than 4.95 s

f ­ and less than 6.05 s

Fig.11

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

REV: 1.0

20

2002.01.30.

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