HT9480(1998) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT9480
(Rev.:1998)

Pager Controller

Holtek Semiconductor 

HT9480

ready interrupt bit (DR; bit 7 of 1EH). Once the

data ready interrupt is triggered, the stack is

not full, and the EMI bit is set, a subroutine call

to location 04H will occur. The related interrupt

request flag (EIF) will, however, be reset, and

the EMI bit cleared to disable further inter-

rupts. This interrupt should be processed care-

fully if the battery fail interrupt is activated as

well.

The battery fail interrupt, on the other hand, is

triggered by a high to low transition on BAF.

When the battery fail interrupt is enabled, the

stack is not full, and the interrupt request flag

(EIF; bit 4 of INTC) is set, a subroutine call to

location 04H will occur. The related interrupt

request flag (EIF) will also be reset, and the

EMI bit be cleared to disable other interrupts.

The programmable timer interrupt is automat-

ically triggered at a rate of 256Hz/N (where the

value of N ranges from 1 to 256), and then the

interrupt request flag (T0F; bit 5 of INTC) is

set. When the timer interrupt is enabled, the

stack is not full, and the programmable timer

interrupt is activated, a subroutine call to loca-

tion 08H will occur. Then, the related interrupt

request flag (T0F) will be reset, and the EMI bit

cleared to disable other interrupts.

The timer/event counter interrupt is initialized

by setting the timer/event counter interrupt re-

quest flag (T1F; bit 6 of INTC), which is nor-

mally caused by a timer overflow. When the

interrupt is enabled, the stack is not full, and

the T1F bit is set, a subroutine call to location

0CH will occur. The related interrupt request

flag (T1F) will be reset, and the EMI bit cleared

to disable further interrupts.

During the execution of an interrupt subrou-

tine, other interrupt acknowledgments are all

held until the “RETI” instruction is executed, or

the EMI bit and the related interrupt control bit

are both set to 1 (if the stack is not full). To

return from the interrupt subroutine, a “RET”

or “RETI” instruction may be invoked. RETI

will set the EMI bit to enable an interrupt service,

but RET will not.

The interrupts are serviced between the rising

edges of the two adjacent T2 clocks. In case of

simultaneous requests, the following table

shows the priority that is applied. These can be

masked by resetting the EMI bit.

Register

INTC

(0BH)

Bit No. Label

0 EMI

1 EEI

2 ET0I

3 ET1I

4 EIF

5 T0F

6 T1F

7

--

Function

Controls the master (global) interrupt

(1=enabled; 0=disabled)

Controls the data ready and battery fail interrupts

(1=enabled; 0=disabled)

Controls the programmable timer interrupt

(1=enabled; 0=disabled)

Controls the timer/event counter interrupt

(1=enabled, 0=disabled)

Internal data ready and battery fail interrupt request flag

(1=active; 0=inactive)

Internal programmable timer interrupt request flag

(1=active; 0=inactive)

Timer/event counter request flag

(1=active; 0=inactive)

Unused bit, read as “0”

INTC register

13

23th Feb ’98

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