HT9480(1998) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT9480
(Rev.:1998)

Pager Controller

Holtek Semiconductor 

HT9480

System clock oscillator

An external clock can also be applied to OSC1.

In this application, the mask option for the

crystal type oscillator should be selected, and

OSC2 kept open.

The low power crystal oscillator is designed for

the pager subsystem and is used to clock the

frequency divider, pager decoder, and LCD

driver. When the system enters the powerdown

mode the crystal oscillator for the pager subsys-

tem keeps running.

Watchdog timer – WDT

The clock source of the watchdog timer (WDT)

is implemented by a subsystem clock

(WDTCLK from the pager subsystem which re-

mains running during a system halt) or by an

WS2

0

0

0

0

1

1

1

1

Division Ratio Option

WS1

WS0 Division Ratio

0

0

1:1

0

1

1:2

1

0

1:4

1

1

1:8

0

0

1:16

0

1

1:32

1

0

1:64

1

1

1:128

instruction clock (the system clock divided by

4), that is decided by mask option. The value of

WDTCLK can be set as 153.6kHz/1024 (or 2048),

76.8kHz/1024 (or 2048), or 32.768kHz/1024 (or

2048), depending upon the different crystal

type. The WDT is the program designed to

avoid software malfunctions or sequence from

jumping to an unknown location with unpre-

dictable results. It can be disabled by mask

option. If the WDT is disabled, all the execu-

tions related to the WDT lead to no operations.

If the subsystem clock is selected, it is first

divided by 256 (8 stages) to get the nominal

time-out period. Longer time-outs can be real-

ized by invoking the WDT prescaler. Writing

data to WS2, WS1, and WS0 (bits 2,1,0 of the

WDTS) can yield different time-out periods. If

the values of WS2, WS1, and WS0 are all equal

to 1, the division ratio is up to 1:128.

On the other hand, if the instruction clock is

applied, the WDT operates in the same manner

as the case when the subsystem clock is chosen,

except that in the HALT state the WDT stops

counting and lose its protection purpose. In this

situation, the WDT logic can be restarted by

external logic. The high nibble and bit 3 of the

WDTS is reserved for user defined flags, which

can be used to indicate some specified status.

The overflow of the WDT under normal opera-

tion not only initializes the “chip reset”, but sets

the status bit “TO”. An overflow in the HALT

Crystal Type and Time-Out Period

153.6kHz

76.8kHz

32.768kHz

13.3ms

26.7ms

62.5ms

26.7ms

53.3ms

125ms

53.3ms

106.7ms

250ms

106.7ms

213.3ms

500ms

213.3ms

426.7ms

1000ms

426.7ms

853.3ms

2000ms

853.3ms

1706.7ms

4000ms

1706.7ms

3413.3ms

8000ms

WDTs register

15

23th Feb ’98

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