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SAA6588

RDS/RBDS pre-processor

Philips Electronics 

Philips Semiconductors

RDS/RBDS pre-processor

Product specification

SAA6588

I2C-BUS INTERFACE REGISTERS

The I2C-bus interface is connected to other blocks of the

pre-processor via internal registers (byte oriented). Those

can either be written by the pre-processor control and read

by the main controller I2C-bus or vice versa.

The device provides 3 input control registers to which may

be written via the I2C-bus and 7 output registers which

may be read via the I2C-bus.

The decoder control updates the output registers after the

detection of a new RDS/RBDS information block and

reads the new mode control settings of the input control

registers. Both operations may occur in the same time slot,

provided that the read operation is complete before a new

RDS/RBDS data bit is processed by the demodulator.

For the corresponding access the registers are addressed

by two separate register pointers, write-enable and

read-enable signals, which are activated either via the

decoder control or via the I2C-bus interface control.

During a read or write transmission from the I2C-bus the

read/write pointer selects the register of the first byte for

transmission and is auto-incremented by the I2C-bus

control for the transfer of subsequent bytes.

During a write transmission after reception of the device

slave address and write bit, the mode control settings for

the pre-processor have to be send in the protocol

sequence as shown in Table 1 and Fig.5.

During a read cycle after reception of the device slave

address and read bit the requested RDS/RBDS data has

to be received in the protocol sequence as given in Table 2

and Fig.7.

Table 1 Input control registers

DATA

Byte 0W

Byte 1W

Byte 2W

FUNCTION

initialization and mode control setting;

see Table 3

pause level and flywheel setting;

see Table 6

pause time/oscillator frequency and

quality detector sensitivity setting;

see Table 7

Table 2 Output registers

DATA

Byte 0R

Byte 1R

Byte 2R

Byte 3R

Byte 4R

Byte 5R

Byte 6R

FUNCTION

decoder and data status information;

see Table 12

last processed block (HIGH byte);

see Table 15

last processed block (LOW byte);

see Table 15

previously processed block (HIGH byte);

see Table 15

previously processed block (LOW byte);

see Table 15

error status information; see Table 15

signal quality indication; see Table 15

WRITE TRANSMISSION FORMAT

Table 3 Description of initialization and mode control

byte (byte 0W)

BIT NAME

FUNCTION

7 SQCM 0: triggered signal quality measurement

1: signal quality continuous measurement

6 TSQD 0: no determination of signal quality

1: trigger of signal quality detector

measurement

5 NWSY 0: normal processing mode

1: restart of synchronization

4 SYM1 selection of error correction mode for

3 SYM0 synchronization search; see Table 4

2 RBDS 0: RDS processing mode

1: RBDS processing mode

1 DAC1 selection of data output protocol and

0 DAC0 indirectly control of data available output

signal (DAVN); see Table 5

1997 Sep 01

11

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