UT1553 데이터 시트보기 (PDF) - Aeroflex UTMC
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UT1553 Datasheet PDF : 40 Pages
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CHANNEL B BIPHASE SIGNALS
NAME
RBO
RBZ
TBO
TBZ
PIN NUMBER
LCC PGA
TYPE ACTIVE
33 K10 TI
--
34 J10 TI
--
30 L10 TO
--
31 K9 TO
--
DESCRIPTION
Receiver (Channel) B One. Manchester data input
from the 1553 bus receiver.
Receiver (Channel) B Zero. This input is the
complement of RBO.
Transmitter (Channel) B One. This Manchester-
encoded output is connected to the 1553 bus
transmitter input. The output is idle low.
Transmitter (Channel) B Zero. This output is the
complement of TBO. The output isidle low.
POWER AND GROUND
NAME
VDD
VSS
PIN NUMBER
LCC PGA
24
L7
43
F9
66 A5
84
E3
1
F3
20
L5
42 F10
62 A7
TYPE ACTIVE
--
--
--
--
DESCRIPTION
+5 VDC Power. Power supply input must be
Reference Ground. Zero VDC logic ground.
3.0 REMOTE TERMINAL ARCHITECTURE
3.1 Internal Registers
The RTMP has six internal registers that allow the host to
control the RTMP’s actions and also to obtain its operational
status. The host can read from or write to three of these
registers: the Time Tag Data Register (TTD), the Control
Register (CTL), and the Base Pointer Data Register (BPD).
Two of the registers are read-only: the Operational Status
Register (OPS), and the Last Command Register (LCM).
The Stop Self-Test Register (SST) is a write-only register.
Six signals allow the host to access the RTMP’s internal
registers. Three of the six signals are control signals: Chip
Select (CS), Read ( RD ), and Write (WR ). The other three
signals are the RTMP’s bidirectional address lines, A0 - A2.
When the CS = 0, the three least significant address lines,
A0 - A2, become inputs to the RTMP. The RTMP decodes
these three address lines, along with C S, RD , and W R, to
determine which of the six internal registers the host is
attempting to access. Table 1 shows the addresses for the
RTMP’s internal registers for read and write operations.
3.2 Read/Write Registers
The RTMP has three internal read/write registers. These
three registers are:
• The Time Tag Data Register
• The Control Register
• The Base Pointer Data Register
Time Tag Data Register (TTD)
The TTD contains a free-running, 16-bit, ripple counter.
The Time Tag clock has a resolution of 64ms. The TTD is
initialized to 0000H when the host asserts the RESET input.
All TTD bits are programmable by performing a write to
the TTD with the desired bit pattern.
The RTMP stores the TTD’s value in the shared memory
area at the end of each 1553 receive message. The host can
also directly read the TTD. Since the TTD is a free-running
counter, the host may read the TTD while the counter is
rippling, resulting in the host reading erroneous data. If this
situation presents a problem, the host should read the TTD
data twice. Figure 5 represents the TTD. (0000H after
Master Reset.)
RTMP-11
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