CDP68HC68S1 데이터 시트보기 (PDF) - Intersil

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CDP68HC68S1

Serial Multiplexed Bus Interface

Intersil 

CDP68HC68S1

delay. Fortunately, SCl ports exhibit an inherent delay between

the loading of the transmit data buffer and the actual beginning

of the start bit appearing on the TXD pin. This delay, at 7812.5

Baud, can be as long as 256 SBl chip internal clock periods

and can be used to synchronize SCl users with SPI and Buff-

ered SPI users to ensure impartial bus arbitration. The delay for

a particular microcomputer must be determined by the user. If

this inherent delay is less than 256 clock periods, then the user

must delay the loading of the first byte enough to ensure that

the total delay including the inherent delay of the SCl port is 256

clock periods.

Framing Errors

While in the SCl mode, the SBI chip is capable of detecting

incoming framing errors. It will do this even though the

incoming signal is also echoed to the user microcomputer,

which should also detect the framing error via its’ UART.

When a framing error is detected by the SBl chip, the gener-

ation of the SCK pulses is terminated until and End Of Mes-

sage is detected.

The SPI Mode Hardware

MCU

TxD

RxD

PAO

SBIC

XMIT BUS+

REC

BUS-

IDLE

MODE CS

DIFFERENTIAL

BUS

+VDD

FIGURE 9. USING THE SCI MODE

Monitoring the IDLE Pin

The user microcomputer must monitor the IDLE pin on the SBlC

chip in order to determine when a message ends, when the next

received byte is a Msg ID byte, and when to attempt arbitration

if the user microcomputer has a message to transmit.

The Master Out Slave In, (MOSl), and Master In Slave Out,

(MISO), pins on the user microcomputer are connected to

the REC and XMlT pins of the SBl chip, respectively, as

shown in Figure 10. The SCK pins on the user microcom-

puter and the SBl chip are connected together. Synchroniza-

tion of data transferred between the user microcomputer and

the SBl chip is done by using the SCK signal provided by the

SBl chip.

In the SPl mode of operation the SBl chip should always be

properly mode selected. This may be accomplished either

by a user microcomputer output signal or by permanent wir-

ing in order to guarantee that the SBl chip will always be

able to receive messages from other microcomputers on the

bus, which may happen at random. To select the SPl mode,

set the MODE pin to a logic l and the CS pin to a logic 0.

The user microcomputer must be able to both detect when

the IDLE signal goes from high to low and sense at other

times whether it is either high or low. Detecting the change

from high to low is necessary in order to know exactly when

the bus goes idle. An MCU can then begin bus arbitration by

attempting to transmit. Being able to sense the level of IDLE

is necessary in order to be able to start transmitting a mes-

sage sometime after IDLE has gone low but no other user on

the bus has had a message to transmit for a length of time.

Instead of polling the IDLE pin via an MCU input pin, the

user may wish to conserve CPU time by using interrupts to

monitor bus activity. The user microcomputer’s external

interrupt pin (IRQ) can be used to edge detect the IDLE pin

for high to low transitions.

Using 68HC05 SCl Port Flags

During message reception, the 68HC05 SCl port receive

data register full flag (RDRF), and optionally its associated

interrupt, can be used by the user microcomputer to deter-

mine when to unload the next received byte.

The user may wish to ignore the RDRF flag and disable the

RDRF interrupt during reception of an unwanted message.

In this case the user can merely wait for the IDLE pin to go

low before attempting any further actions.

The normally available transmit data register empty flag

(TDRE) can be used to determine when to load the next byte

to be transmitted onto the bus. If there are no more bytes to

be transmitted, then consider the last message as having

been transmitted, and generate an End Of Message (EOM)

(i.e. transmit a logic 1 for 10 contiguous bit times by creating

a software delay).

MCU

MISO

MOSI

SCK

SS

PAO

PA1

SBIC

XMIT BUS+

REC

BUS-

SCK

VSS

IDLE

CONTROL

DIFFERENTIAL

BUS

MODE CS

+VDD

VSS

FIGURE 10. USING THE SPI MODE

The user microcomputer should configure its SPl port for

slave mode operation with SCK positive polarity and data

transfer on SCK leading edge (i.e. CPOL = 0, CPHA = 1, for

68HC05 microcomputers). 8-bit data transfers between the

user microcomputer and the SBl chip occur at differential

bus transfer speed.

In the SPI mode, the user microcomputer operates in the

slave mode and the SBl chip operates as the master. The

SS pin on the user microcomputer must be wired low or

forced low whenever the SBl chip has incoming data. It may

be useful to connect the CONTROL pin of the SBl chip to the

Slave Select (SS) pin of the 68HC05 microcomputer. The

SBl chip will then control the user microcomputer’s SPI port.

The user microcomputer can request transmission of data

onto the bus by the SBl chip by loading data into its SPl data

register and then pulling the SBlC’s CONTROL pin low (for

at least 1µs). However, it must do so before the SBl chip has

begun to receive data from another MCU.

6-94

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