LTC1292 데이터 시트보기 (PDF) - Linear Technology

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LTC1292

Single Chip 12-Bit Data Acquisition Systems

Linear Technology 

APPLICATI S I FOR ATIO

LTC1292/LTC1297

ANALOG

INPUTS

LTC1297

CS

CLK

DOUT

MC68HC11

DO

SCK

MISO

DOUT FROM LTC1297 STORED ON MC68HC11 RAM

MSB

LOCATION #61 O O O O B11 B10 B9 B8 BYTE 1

LOCATION #62

B7 B6 B5 B4 B3

B2 B1 B0 BYTE 2

LTC1292/7 F04

Figure 4. Hardware and Software Interface to Motorola MC68HC11 Microcontroller

MC68HC11 CODE for LTC1297 Interface

LABEL MNEMONIC

LDAA

STAA

LDAA

STAA

LDAA

OPERAND

#$50

$1028

#$1B

$1009

#$00

STAA

LOOP LDX

$50

#$1000

LDAB

LDAA

BCLR

NOP

NOP

NOP

STAA

#$00

$50

$08,X,$01

$102A

COMMENTS

CONFIGURATION DATA FOR SPCR

LOAD DATA INTO SPCR ($1028)

CONFIG. DATA FOR PORT D DDR

LOAD DATA INTO PORT D DDR

LOAD DUMMY DIN WORD INTO

ACC A

LOAD DUMMY DIN DATA INTO $0

LOAD INDEX REGISTER X WITH

$1000

LOAD ACC B WITH $00

LOAD DIN INTO ACC FROM $50

D0 GOES LOW (CS GOES LOW)

3 NOP FOR tsuCS TIMING

LOAD DUMMY DIN INTO SPI,

START CLK

LABEL MNEMONIC

LOOP1 LDAA

BPL

LDAA

STAA

STAA

OPERAND

$1029

LOOP1

$102A

$61

$102A

LOOP2 LDAA

BPL

BSET

LDAA

STAA

ROR

ROR

ROR

ROR

JMP

$1029

LOOP2

$08X,$01

$102A

$62

$61

$62

$61

$62

LOOP

COMMENTS

CHECK SPI STATUS REG

CHECK IF TRANSFER IS DONE

LOAD LTC1297 MSBs INTO ACC A

STORE MSBs IN $61

LOAD DUMMY DIN INTO SPI,

START SCK

CHECK SPI STATUS RES

CHECK IF TRANSFER IS DONE

D0 GOES HIGH (CS GOES HIGH)

LOAD LTC1297 LSBs INTO ACC A

STORE LSBs IN $62

ROTATE RIGHT WITH CARRY

NEEDED TO RIGHT JUSTIFY

THE DATA IN $61 AND $62

START NEXT CONVERSION

The data is right- justified in the two memory locations by

rotating right twice (Figure 4). ANDing the first byte with

0FHEX clears the four most significant bits. This operation

was not included in the code. It can be inserted in the data

gathering loop or outside the loop when the data is

processed.

Interfacing to the Parallel Port of the Intel 8051 Family

The Intel 8051 has been chosen to show the interface

between the LTC1292/LTC1297 and parallel port

microprocessors. The signals CS and CLK are generated

on two port lines and the DOUT signal is read on a third port

line. After a falling CLK edge each data bit is loaded into the

carry bit and then rotated into the accumulator. Once the

first 8 MSBs have been shifted into the accumulator they

are loaded into register R2. The last four bits are shifted in

the same way and loaded into register R3. The output data

is left-justified in registers R2 and R3 (Figure 5).

For the LTC1297 four NOPs need to be inserted in the 8051

code after CS goes low to allow the LTC1297 to wake up

from power shutdown (tsuCS).

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