E28F004B5-B60 데이터 시트보기 (PDF) - Intel

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E28F004B5-B60

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

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SMART 5 BOOT BLOCK MEMORY FAMILY

these bits, several operations (such as cumulatively

erasing multiple blocks or programming several

bytes in sequence) may be performed before

polling the status register to determine if an error

occurred during the series.

Issue the Clear Status Register command (50H) to

clear the status register. It functions independently

of the applied VPP voltage and RP# can be VIH or

VHH. This command is not functional during block

erase suspend modes. Resetting the part with RP#

also clears the status register.

3.2.4

WORD/BYTE PROGRAM

Word or byte program operations are executed by a

two-cycle command sequence. Program Set-Up

(40H) is issued, followed by a second write that

specifies the address and data (latched on the

rising edge of WE# or CE#, whichever comes first).

The WSM then takes over, controlling the program

and program verify algorithms internally. While the

WSM is working, the device automatically enters

read status register mode and remains there after

the word/byte program is complete. (see Figure 8).

The completion of the program event is indicated on

status register bit SR.7.

When a word/byte program is complete, check

status register bit SR.4 for an error flag (“1”). The

cause of a failure may be found on SR.3, which

indicates “1” if VPP was out of program/erase

voltage range (VPPH1 or VPPH2). The status register

should be cleared before the next operation. The

internal WSM verify only detects errors for “1”s that

do not successfully write to “0”s.

Since the device remains in status register read

mode after programming is completed, a command

must be issued to switch to another mode before

beginning a different operation.

3.2.5

BLOCK ERASE

A block erase changes all block data to 1’s

(FFFFH) and is initiated by a two-cycle command.

An Erase Set-Up command (20H) is issued first,

followed by an Erase Confirm command (D0H)

along with an address within the target block. The

address will be latched at the rising edge of WE# or

CE#, whichever comes first.

Internally, the WSM will program all bits in the block

to “0,” verify all bits are adequately programmed to

ADVANCE INFORMATION

“0,” erase all bits to “1,” and verify that all bits in the

block are sufficiently erased. After block erase

command sequence is issued, the device

automatically enters read status register mode and

outputs status register data when read (see

Figure 9). The completion of the erase event is

indicated on status register bit SR.7.

When an erase is complete, check status register

bit SR.5 for an error flag (“1”). The cause of a failure

may be found on SR.3, which indicates “1” if VPP

was out of program/erase voltage range (VPPH1 or

VPPH2). If an Erase Set-Up (20H) command is

issued but not followed by an Erase Confirm (D0H)

command, then both the program status (SR.4) and

the erase status (SR.5) will be set to “1.”

The status register should be cleared before the

next operation. Since the device remains in status

register read mode after erasing is completed, a

command must be issued to switch to another

mode before beginning a different operation.

3.2.5.1

Erase Suspend/Resume

The Erase Suspend command (B0H) interrupts an

erase operation in order to read data in another

block of memory. While the erase is in progress,

issuing the Erase Suspend command requests that

the WSM suspend the erase algorithm after a

certain latency period. After issuing the Erase

Suspend command, write the Read Status Register

command, then check bit SR.7 and SR.6 to ensure

the device is in the erase suspend mode (both will

be set to “1”). This check is necessary because the

WSM may have completed the erase operation

before the Erase Suspend command was issued. If

this occurs, the Erase Suspend command would

switch the device into read array mode. See

Appendix A for a comprehensive chart showing the

state transitions.

When erase has been suspended, a Read Array

command (FFH) can be written to read from blocks

other than that which is suspended. The only other

valid commands at this time are Erase Resume

(D0H) or Read Status Register.

During erase suspend mode, the chip can go into a

pseudo-standby mode by taking CE# to VIH, which

reduces active current draw. VPP must remain at

VPPH1 or VPPH2 (the same VPP level used for block

erase) while erase is suspended. RP# must also

remain at VIH or VHH (the same RP# level used for

block erase).

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