E28F004B5-B60 데이터 시트보기 (PDF) - Intel

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E28F004B5-B60

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

E

SMART 5 BOOT BLOCK MEMORY FAMILY

Start

Write 40H,

Word/Byte Address

Write Word/Byte

Data/Address

Read

Status Register

NO

SR.7 = 1

?

YES

Full Status

Check if Desired

Word/Byte Program

Complete

Bus

Operation

Write

Write

Command

Comments

Setup

Program

Data = 40H

Addr = Word/Byte to Program

Program

Data = Data to Program

Addr = Location to Program

Read

Status Register Data

Toggle CE# or OE#

to Update SRD.

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

Repeat for subsequent word/byte program operations.

SR Full Status Check can be done after each word/byte

program operation, or after a sequence of word/byte programs.

Write FFH after the last program operation to reset device to

read array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

1

SR.3 =

0

1

SR.4 =

0

Word/Byte Program

Successful

VPP Range Error

Word/Byte Program

Error

Bus

Operation

Standby

Command

Comments

Check SR.3

1 = VPP Low Detect

Standby

Check SR.4

1 = Word Byte Program Error

SR.3 MUST be cleared, if set during a program attempt,

before further attempts are allowed by the Write State Machine.

SR.4 is only cleared by the Clear Status Register Command, in cases

where multiple bytes are programmed before full status is checked.

If error is detected, clear the Status Register before attempting

retry or other error recovery.

0599-07

Figure 8. Automated Word/Byte Program Flowchart

ADVANCE INFORMATION

21

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