E28F004B5-B60 데이터 시트보기 (PDF) - Intel
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E28F004B5-B60 Datasheet PDF : 38 Pages
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SMART 5 BOOT BLOCK MEMORY FAMILY
E
Table 7. Status Register Bit Definition
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready
(WSMS)
0 = Busy
Check WSM bit first to determine word/byte
program or block erase completion, before
checking program or erase status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
When this bit is set to “1,” one of the following has
occurred:
1. VPP out of range.
2. WSM has applied the max number of erase
pulses to the block and is still unable to verify
successful block erasure.
3. Erase Set-Up command was followed by a
command other than Erase Confirm.
When this bit is set to “1,” one of the following has
occurred:
1. VPP out of range.
2. WSM has applied the max number of program
pulses and is still unable to verify a successful
program.
3. Erase Set-Up command was followed by a
command other than Erase Confirm.
The VPP status bit does not provide continuous
indication of VPP level. The WSM interrogates VPP
level only after the Program or Erase command
sequences have been entered, and informs the
system if VPP is out of range. The VPP status bit is
not guaranteed to report accurate feedback
between VPPLK and VPPH.
SR.2–SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and should
be masked out when polling the status register.
20
ADVANCE INFORMATION
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