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ISP1581

Universal serial bus 2.0 high-speed interface device

Philips Electronics 

Philips Semiconductors

ISP1581

USB 2.0 HS interface device

9397 750 09665

Product data

7.1 USB 2.0 transceiver

The analog transceiver interfaces directly to the USB cable via integrated termination

resistors. The high-speed transceiver requires an external resistor (12.0 kΩ ± 1%)

between pin RREF and ground to ensure an accurate current mirror that is used to

generate the USB 2.0 current drive. A full-speed transceiver is integrated as well.

This makes the ISP1581 compliant with USB 2.0 and USB 1.1, supporting both the

high-speed and full-speed physical layer. After automatic speed detection, the Philips

Serial Interface Engine sets the transceiver to use either high-speed or full-speed

signaling.

7.2 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no firmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit (de-)stuffing, CRC

checking/generation, Packet IDentifier (PID) verification/generation, address

recognition, handshake evaluation/generation.

7.3 Philips HS (High-Speed) Transceiver

7.3.1 Philips Parallel Interface Engine

In the HS Transceiver, The Philips PIE interface uses a 16 bit Parallel bi-directional

data interface. The functions of the HS (High-speed) module also include

Bit-stuffing/De-stuffing and NRZI Encoding/Decoding logic.

7.3.2 Peripheral circuit

To maintain a constant current driver for HS (High-Speed) transmit circuits and to bias

other analog circuits, an internal band-gap reference circuit and RREF resistor are

used to form the reference current. This circuit requires an external precision resistor

(12.0 kΩ ± 1%) connected to analog ground.

7.3.3 HS detection

ISP1581 handles more than one electrical state (FS/HS) under the USB

specification. When the USB cable is connected from the device to the host

controller, at first the device ISP1581 defaults to the Full-speed (FS) state until it sees

a bus reset from the host controller.

During the bus reset, the device initiates a HS chirp to detect whether the

host-controller supports USB 2.0 or USB 1.1. Chirping must be done with the pull-up

resistor connected and the internal termination resistors disabled. If the HS

handshake shows that there is a HS host connected, then ISP1581 switches to the

HS state.

In HS state, the ISP1581 observes the bus for periodic activity. If the bus remains

inactive for 3 ms, the device switches to the FS state to check for an

SE0(Single-ended zero) condition on the USB bus. If an SE0 condition is detected for

the designated time window(100 µs to 875 µs, see section 7.1.7.6 of the USB

specification Rev. 2.0), the ISP1581 switches to the HS chirp state again to do a HS

detection handshake. Otherwise, the ISP1581 remains in the FS state adhering to the

bus-suspend specification.

Rev. 04 — 18 July 2002

© Koninklijke Philips Electronics N.V. 2002. All rights reserved.

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