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ISP1581 Datasheet PDF : 80 Pages
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Philips Semiconductors
ISP1581
USB 2.0 HS interface device
All data IN transactions use the Transmit buffers (TX), which are handled by the
DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which
are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,
OUT and SETUP) are handled by the CDBGMOD bits.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, Setup and High Speed Status) can also be controlled individually. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in
Table 12.
Table 12: Interrupt Enable register: bit allocation
Bit
31
30
29
28
Symbol
reserved
Reset
-
-
-
-
Bus Reset
-
-
-
-
Access
R/W
R/W
R/W
R/W
Bit
23
22
21
20
Symbol
IEP6TX IEP6RX
IEP5TX
IEP5RX
Reset
0
0
0
0
Bus Reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
Bit
15
14
13
12
Symbol
IEP2TX IEP2RX
IEP1TX
IEP1RX
Reset
0
0
0
0
Bus Reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
Bit
7
6
5
4
Symbol
reserved IEDMA IEHS_STA IERESM
Reset
-
0
0
0
Bus Reset
-
0
0
0
Access
R/W
R/W
R/W
R/W
27
-
-
R/W
19
IEP4TX
0
0
R/W
11
IEP0TX
0
0
R/W
3
IESUSP
0
0
R/W
26
-
-
R/W
18
IEP4RX
0
0
R/W
10
IEP0RX
0
0
R/W
2
IEPSOF
0
0
R/W
25
IEP7TX
0
0
R/W
17
IEP3TX
0
0
R/W
9
reserved
-
-
R/W
1
IESOF
0
0
R/W
24
IEP7RX
0
0
R/W
16
IEP3RX
0
0
R/W
8
IEP0SETUP
0
0
R/W
0
IEBRST
0
unchanged
R/W
Table 13: Interrupt Enable register: bit description
Bit
Symbol
Description
31 to 26 -
reserved; must write logic 0
25 to 12
IEP7TX to
IEP1RX
A logic 1 enables interrupt from the indicated endpoint.
11
IEP0TX
A logic 1 enables interrupt from the Control IN endpoint 0.
10
IEP0RX
A logic 1 enables interrupt from the Control OUT endpoint 0.
9
-
reserved
8
IEP0SETUP A logic 1 enables the interrupt for the Setup data received on
endpoint 0.
7
-
reserved
9397 750 09665
Product data
Rev. 04 — 18 July 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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