28F004B5 데이터 시트보기 (PDF) - Intel

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28F004B5

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

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SMART 5 BOOT BLOCK MEMORY FAMILY

3.0 PRINCIPLES OF OPERATION

The system processor accesses the Smart 5 boot

block memories through the Command User

Interface (CUI), which accepts commands written

with standard microprocessor write timings and

TTL-level control inputs. The flash can be switched

into each of its three read and two write modes

through commands issued to the CUI. A

comprehensive chart showing the state transitions

is in Appendix A.

After initial device power-up or return from deep

power-down mode, the device defaults to read

array mode. In this mode, manipulation of the

memory control pins allows array read, standby,

and output disable operations. The other read

modes, read identifier and read status register, can

be reached by issuing the appropriate command to

the CUI. Array data, identifier codes and status

register results can be accessed using these

commands independently from the VPP voltage.

Read identifier mode can also be accessed by

PROM programming equipment by raising A9 to

high voltage (VID).

CUI commands sequences also control the write

functions of the flash memory, Program and Erase.

Issuing program or erase command sequences

internally latches addresses and data and initiates

Write State Machine (WSM) operations to execute

the requested write function. The WSM internally

regulates the program and erase algorithms,

including pulse repetition, internal verification, and

margining of data, freeing the host processor from

these tasks and allowing precise control for high

reliability. To execute Program or Erase

commands, VPP must be at valid write voltage (5 V

or 12 V).

While the WSM is executing a program operation,

the device defaults to the read status register mode

and all commands are ignored. Thus during the

programming process, only status register data can

be accessed from the device. While the WSM is

executing a erase operation, the device also

defaults to the read status register mode but one

additional command is available, erase suspend to

read, which will suspend the erase operation and

allow reading of array data. The suspended erase

operation can be completed by issuing the Erase

Resume command. After the program or erase

operation has completed, the device remains in

read status register mode. From this mode any of

the other read or write modes can be reached with

the appropriate command. For example, to read

data, issue the Read Array command. Additional

Program or Erase commands can also be issued

from this state.

During program or erase operations, the array data

is not available for reading or code execution,

except during an erase suspend. Consequently, the

software that initiates and polls progress of program

and erase operations must be copied to and

executed from system RAM during flash memory

update. After successful completion, reads are

again possible via the Read Array command.

Each of the device modes will be discussed in

detail in the following sections.

3.1 Bus Operations

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

Four control pins dictate the data flow in and out of

the component: CE#, OE#, WE#, and RP#. These

bus operations are summarized in Tables 3 and 4.

3.1.1

READ

The flash memory has three read modes available,

read array, read identifier, and read status. These

read modes are accessible independent of the VPP

voltage. RP# can be at either VIH or VHH. The

appropriate read-mode command must be issued to

the CUI to enter the corresponding mode. Upon

initial device power-up or after exit from deep

power-down mode, the device automatically

defaults to read array mode.

CE# and OE# must be driven active to obtain data

at the outputs. CE# is the device selection control,

and, when active, enables the selected memory

device. OE# is the data output (DQ0–DQ15) control

and when active drives the selected memory data

onto the I/O bus. In read modes, WE# must be at

VIH and RP# must be at VIH or VHH. Figure 15

illustrates a read cycle.

ADVANCE INFORMATION

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