28F004B5 데이터 시트보기 (PDF) - Intel

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28F004B5

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

SMART 5 BOOT BLOCK MEMORY FAMILY

E

3.1.2

OUTPUT DISABLE

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins (if available on

the device) DQ0–DQ15 are placed in a high-

impedance state.

3.1.3

STANDBY

Deselecting the device by bringing CE# to a logic-

high level (VIH) places the device in standby mode

which substantially reduces device power

consumption. In standby, outputs DQ0–DQ15 are

placed in a high-impedance state independent of

OE#. If deselected during program or erase

operation, the device continues functioning and

consuming active power until the operation

completes.

3.1.4

WORD/BYTE CONFIGURATION

The 16-bit devices can be configured for either an

8-bit or 16-bit bus width by setting the BYTE# pin

before power-up. This is not applicable to the 8-bit

only E28F004B5.

When BYTE# is set to logic low, the byte-wide

mode is enabled, where data is read and

programmed on DQ0–DQ7 and DQ15/A–1 becomes

the lowest order address that decodes between the

upper and lower byte. DQ8–DQ14 are tri-stated

during the byte-wide mode.

When BYTE# is at logic high, the word-wide mode

is enabled, and data is read and programmed on

DQ0–DQ15.

3.1.5

DEEP POWER-DOWN/RESET

RP# at VIL initiates the deep power-down mode,

also referred to as reset mode.

From read mode, RP# going low for time tPLPH

deselects the memory, places output drivers in a

high-impedance state, and turns off all internal

circuits. After return from power-down, a time tPHQV

is required until the initial memory access outputs

are valid. A delay (tPHWL or tPHEL) is required after

return from power-down before a write can be

initiated. After this wake-up interval, normal

operation is restored. The CUI resets to read array

mode, and the status register is set to 80H. This

case is shown in Figure 14A.

If RP# is taken low for time tPLPH during a program

or erase operation, the operation will be aborted

and the memory contents at the aborted location

(for a program) or block (for an erase) are no longer

valid, since the data may be partially erased or

written. The abort process goes through the

following sequence: When RP# goes low, the

device shuts down the operation in progress, a

process which takes time tPLRH to complete. After

this time tPLRH, the part will either reset to read

array mode (if RP# has gone high during tPLRH,

Figure 14B) or enter deep power-down mode (if

RP# is still logic low after tPLRH, Figure 14C). In

both cases, after returning from an aborted

operation, the relevant time tPHQV or tPHWL/tPHEL

must be waited before a read or write operation is

initiated, as discussed in the previous paragraph.

However, in this case, these delays are referenced

to the end of tPLRH rather than when RP# goes high.

As with any automated device, it is important to

assert RP# during system reset. When the system

comes out of reset, processor expects to read from

the flash memory. Automated flash memories

provide status information when read during

program or block erase operations. If a CPU reset

occurs with no flash memory reset, proper CPU

initialization may not occur because the flash

memory may be providing status information

instead of array data. Intel’s Flash memories allow

proper CPU initialization following a system reset

through the use of the RP# input. In this application,

RP# is controlled by the same RESET# signal that

resets the system CPU.

3.1.6

WRITE

The CUI does not occupy an addressable memory

location. Instead, commands are written into the

CUI using standard microprocessor write timings

when WE# and CE# are low, OE# = VIH, and the

proper address and data (command) are presented.

The address and data for a command are latched

on the rising edge of WE# or CE#, whichever goes

high first. Figure 16 illustrates a write operation.

14

ADVANCE INFORMATION

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