IMC010FLSA-ET15 데이터 시트보기 (PDF) - Intel

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IMC010FLSA-ET15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

Bus

Operation

Write

Command

Suspend

Erase

x8 Mode

Data e B0H

Address e Desired

Block to Erase

Suspend

x16 Mode

Data e B0B0H

Address e Desired

Block Pair to Erase

Suspend

Read

Standby

Standby

Write

Status Register

Data Toggle OE

CE1 or CE2 to

update Status

Register

Check SR Bit 7

1 e Ready

0 e Busy

Status Register

Data Toggle OE or

(CE1 and CE2 )

to update Status

Register

Check SR Bit 7 and 15

1 e Ready

0 e Busy

Rd Array

Cmd

Check SR Bit 6

1 e Suspended

0 e In Progress

Data e FFH

Check SR Bit 6 and 14

1 e Suspended

0 e In Progress

Data e FFFFH

Read

Read Data

until finished

Read Data

until finished

Write

Erase

Resume

Data e D0H

Address e Valid

Block Address

Data e D0D0H

Address e Valid

Block Pair Address

290434 – 27

Figure 15 Erase Suspend Resume Algorithm Allows Reads to Interrupt Erases

POWER CONSUMPTION

STANDBY MODE

In most applications software will only be accessing

one device pair at a time The Series 2 Card is de-

fined to be in the standby mode when one device

pair is in the Read Array Mode while the remaining

devices are in the Deep-Sleep Mode The Series 2

Card’s CE1 and CE2 input signals must also be

at VIH In standby mode much of the card’s circuitry

is shut off substantially reducing power consump-

tion Typical power consumption for a 20 Megabyte

Series 2 card in standby mode is 65 mA

SLEEP MODE

Writing a ‘‘1’’ to the PWRDWN bit of the GLOBAL

POWERDOWN REGISTER places all FlashFile

Memory devices into a Deep-Sleep mode This dis-

ables most of the 28F008SA’s circuitry and reduces

current consumption to 0 2 mA per device Addition-

ally when the host system pulls ASIC control logic

high and latches all address and data lines (i e not

toggling) the card’s total current draw is reduced to

approximately 5 mA (CMOS input levels) for a 20

Megabyte card On writing a ‘‘0’’ to the PWRDWN bit

(Global PowerDown Register) or any individual de-

vice pair (Sleep Control Register) a Deep-Sleep

mode recovery period must be allowed for

28F008SA device circuitry to power back on

22

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