LH28F800BGB-BL85 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800BGB-BL85 Datasheet PDF : 43 Pages
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4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase or word write, the device will not
recognize the Read Array command until the WSM
completes its operation unless the WSM is
suspended via an Erase Suspend or Word Write
Suspend command. The Read Array command
functions independently of the VPP voltage and
RP# can be VIH or VHH.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture and device codes
(see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read Identifier Codes command functions
independently of the VPP voltage and RP# can be
VIH or VHH. Following the Read Identifier Codes
command, the following information can be read :
Table 4 Identifier Codes
CODE
ADDRESS
Manufacture Code
00000H
Device Code (Top Boot)
00001H
Device Code (Bottom Boot) 00001H
DATA
00B0H
0060H
0062H
4.3 Read Status Register Command
The status register may be read to determine when
a block erase or word write is complete and
whether the operation completed successfully. It
may be read at any time by writing the Read Status
Register command. After writing this command, all
subsequent read operations output data from the
status register until another valid command is
written. The status register contents are latched on
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
the falling edge of OE# or CE#, whichever occurs.
OE# or CE# must toggle to VIH before further reads
to update the status register latch. The Read Status
Register command functions independently of the
VPP voltage. RP# can be VIH or VHH.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing
multiple blocks or writing several words in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied VPP voltage. RP# can
be VIH or VHH. This command is not functional
during block erase or word write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFFFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
the device automatically outputs status register data
when read (see Fig. 3). The CPU can detect block
erase completion by analyzing the output data of
the RY/BY# pin or status register bit SR.7.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error
is detected, the status register should be cleared
before system software attempts corrective actions.
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