LH28F800BGB-BL85 데이터 시트보기 (PDF) - Sharp Electronics
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LH28F800BGB-BL85 Datasheet PDF : 43 Pages
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The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and RY/BY# will return to VOL. After the Erase
Resume command is written, the device
automatically outputs status register data when
read (see Fig. 5). VPP must remain at VPPH1/2/3
(the same VPP level used for block erase) while
block erase is suspended. RP# must also remain at
VIH or VHH (the same RP# level used for block
erase). WP# must also remain at VIL or VIH (the
same WP# level used for block erase). Block erase
cannot resume until word write operations initiated
during block erase suspend have completed.
4.8 Word Write Suspend Command
The Word Write Suspend command allows word
write interruption to read data in other flash memory
locations. Once the word write process starts,
writing the Word Write Suspend command requests
that the WSM suspend the word write sequence at
a predetermined point in the algorithm. The device
continues to output status register data when read
after the Word Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the word write operation has been
suspended (both will be set to "1"). RY/BY# will
also transition to VOH. Specification tWHRH1 defines
the word write suspend latency.
At this point, a Read Array command can be
written to read data from locations other than that
which is suspended. The only other valid
commands while word write is suspended are Read
Status Register and Word Write Resume. After
Word Write Resume command is written to the
flash memory, the WSM will continue the word
write process. Status register bits SR.2 and SR.7
will automatically clear and RY/BY# will return to
VOL. After the Word Write Resume command is
LH28F800BG-L/BGH-L (FOR TSOP, CSP)
written, the device automatically outputs status
register data when read (see Fig. 6). VPP must
remain at VPPH1/2/3 (the same VPP level used for
word write) while in word write suspend mode. RP#
must also remain at VIH or VHH (the same RP#
level used for word write). WP# must also remain
at VIL or VIH (the same WP# level used for word
write).
4.9 Block Locking
This Boot Block flash memory architecture features
two hardware-lockable boot blocks so that the
kernel code for the system can be kept secure
while other blocks are programmed or erased as
necessary.
4.9.1 VPP = VIL FOR COMPLETE PROTECTION
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device.
4.9.2 WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
boot blocks are lockable. For the bottom
configuration, the bottom two boot blocks are
lockable. Unlocked blocks can be programmed or
erased normally (Unless VPP is below VPPLK).
4.9.3 BLOCK UNLOCKING
WP# = VIH or RP# = VHH unlocks all lockable
blocks.
These blocks can now be programmed or erased.
WP# or RP# controls all block locking and VPP
provides protection against spurious writes. Table 5
defines the write protection methods.
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