MC145170P2 데이터 시트보기 (PDF) - Freescale Semiconductor

부품명

상세내역

제조사

MC145170P2

PLL Frequency Synthesizer with Serial Interface

Freescale Semiconductor 

Pin Connections

When activated, the fR signal appears as normally low and pulses high. The pulse width is 4.5 cycles of

the OSCin pin signal, except when a divide ratio of 1 is selected. When 1 is selected, the OSCin signal is

buffered and appears at the fR pin.

fV

N Counter Output (Pin 10)

This signal is the buffered output of the 16-stage N counter. fV can be enabled or disabled via the C register

(patented). The output is disabled (static low logic level) upon power up. If unused, the output should be

left disabled and unconnected to minimize interference with external circuitry.

The fV signal can be used to verify the N counter's divide ratio. This ratio extends from 40 to 65,535 and

is determined by the binary value loaded into the N register. The maximum frequency which the phase

detectors operate is 2 MHz. Therefore, the frequency of fV must not exceed 2 MHz.

When activated, the fV signal appears as normally low and pulses high.

3.4 Loop Pins

fin

Frequency Input (Pin 4)

This pin is a frequency input from the VCO. This pin feeds the on-chip amplifier which drives the N

counter. This signal is normally sourced from an external voltage-controlled oscillator (VCO), and is

ac-coupled into fin. A 100 pF coupling capacitor is used for measurement purposes and is the minimum

size recommended for applications (see Figure 25). The frequency capability of this input is dependent on

the supply voltage as listed in Table 6, Loop Specifications. For small divide ratios, the maximum

frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited

to a maximum frequency of 2 MHz.)

For signals which swing from at least the VIL to VIH levels listed in Table 3, the Electrical Characteristics

table on page 4, dc coupling may be used. Also, for low frequency signals (less than the minimum

frequencies shown in Table 6 on page 7), dc coupling is a requirement. The N counter is a static counter

and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure

fast rise and fall times into the fin pin. See Figure 25.

Each rising edge on the fin pin causes the N counter to decrement by 1.

PDout

Single-Ended Phase/Frequency Detector Output (Pin 13)

This is a three-state output for use as a loop error signal when combined with an external low-pass filter.

Through use of a patented technique, the detector's dead zone has been eliminated. Therefore, the

phase/frequency detector is characterized by a linear transfer function. The operation of the

phase/frequency detector is described below and is shown in Figure 19.

POL bit (C7) in the C register = low (see Figure 16)

Frequency of fV > fR or Phase of fV Leading fR: negative pulses from high impedance

MC145170-2 Technical Data, Rev. 5

12

Freescale Semiconductor

Share Link: