MC145170P2 데이터 시트보기 (PDF) - Freescale Semiconductor

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MC145170P2

PLL Frequency Synthesizer with Serial Interface

Freescale Semiconductor 

Pin Connections

Frequency of fV < fR or Phase of fV Lagging fR: positive pulses from high impedance

Frequency and Phase of fV = fR: essentially high-impedance state; voltage at pin determined by loop filter

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: positive pulses from high impedance

Frequency of fV < fR or Phase of fV Lagging fR: negative pulses from high impedance

Frequency and Phase of fV = fR: essentially high-impedance state; voltage at pin determined by loop filter

This output can be enabled, disabled, and inverted via the C register. If desired, PDout can be forced to the

high-impedance state by utilization of the disable feature in the C register (patented).

φR and φV

Double-Ended Phase/Frequency Detector Outputs

(Pins 14, 15)

These outputs can be combined externally to generate a loop error signal. Through use of a patented

technique, the detector's dead zone has been eliminated. Therefore, the phase/frequency detector is

characterized by a linear transfer function. The operation of the phase/frequency detector is described

below and is shown in Figure 19.

POL bit (C7) in the C register = low (see Figure 16)

Frequency of fV > fR or Phase of fV Leading fR: φV = negative pulses, φR = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φV = essentially high, φR = negative pulses

Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time

period when both pulse low in phase

POL bit (C7) = high

Frequency of fV > fR or Phase of fV Leading fR: φR = negative pulses, φV = essentially high

Frequency of fV < fR or Phase of fV Lagging fR: φR = essentially high, φV = negative pulses

Frequency and Phase of fV = fR: φV and φR remain essentially high, except for a small minimum time

period when both pulse low in phase

These outputs can be enabled, disabled, and interchanged via the C register (patented).

LD

Lock Detector Output (Pin 11)

This output is essentially at a high level with narrow low-going pulses when the loop is locked (fR and fV

of the same phase and frequency). The output pulses low when fV and fR are out of phase or different

frequencies (see Figure 19).

This output can be enabled and disabled via the C register (patented). Upon power up, on-chip

initialization circuitry disables LD to a static low logic level to prevent a false “lock” signal. If unused, LD

should be disabled and left open.

MC145170-2 Technical Data, Rev. 5

Freescale Semiconductor

13

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