Pin Connections
3.5 Power Supply
VDD
Most Positive Supply Potential (Pin 16)
This pin may range from 2.7 to 5.5 V with respect to VSS.
For optimum performance, VDD should be bypassed to VSS using low-inductance capacitor(s) mounted
very close to the device. Lead lengths on the capacitor(s) should be minimized. (The very fast switching
speed of the device causes current spikes on the power leads.)
VSS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes, the VSS pin is tied to a ground plane.
Power Up
ENB
CLK
123
12345
4 or More Clocks
Din
Don't Cares
Zeroes
One Zero
Don't Cares
Figure 15. Reset Sequence
NOTES: This initialization sequence is usually not necessary because the on-chip power-on reset circuit performs the
initialization function. However, this initialization sequence must be used immediately after power up if control of the CLK
pin is not possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such that the supply voltage to the device is reduced to
below 2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the
on-chip power-on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V.
MC145170-2 Technical Data, Rev. 5
14
Freescale Semiconductor