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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 4 FPGAs

Preliminary Data Sheet

December 2000

Programmable Logic Cells (continued)

As discussed in the Memory Mode section on page 19,

if the SLIC is placed into one of the modes where it

contains both buffers and a decode or AOI function

(e.g., BUF_BUF_DEC mode), the DEC output can be

gated with the 3-state input signal. This allows up to a

6-input decode (e.g., BUF_DEC_DEC mode) plus the

3-state input to control the enable/disable of up to four

buffers per SLIC. Figure 15—Figure 19 show several

configurations of the SLIC, while Table 6 shows all of

the possible modes.

Table 6. SLIC Modes

Mode

No.

Mode

BUF

[3:0]

BUF

[7:4]

BUF

[9:8]

1

BUFFER

Buffer Buffer Buffer

2 BUF_BUF_DEC Buffer Buffer Decoder

3 BUF_DEC_BUF Buffer Decoder Buffer

4 BUF_DEC_DEC Buffer Decoder Decoder

5 DEC_BUF_BUF Decoder Buffer Buffer

6 DEC_BUF_DEC Decoder Buffer Decoder

7 DEC_DEC_BUF Decoder Decoder Buffer

8

DECODER Decoder Decoder Decoder

SIN9

I9

LOGIC 1 OR 0

SIN8

I8

LOGIC 1 OR 0

SOUT09

SOUT08

SIN7

I7

LOGIC 1 OR 0

SIN6

I6

LOGIC 1 OR 0

SIN5

I5

LOGIC 1 OR 0

SIN4

I4

LOGIC 1 OR 0

TRI

0/1

0/1

DEC

SOUT07

SOUT06

SOUT05

SOUT04

DEC

0/1

0/1

SIN3

I3

SOUT03

LOGIC 1 OR 0

SIN2

I2

SOUT02

LOGIC 1 OR 0

SIN1

I1

SOUT01

LOGIC 1 OR 0

SIN0

I0

SOUT00

LOGIC 1 OR 0

5-5744(F).a.

Figure 14. SLIC All Modes Diagram

22

Lucent Technologies Inc.

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