OR4E10 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

Preliminary Data Sheet

December 2000

Embedded Block RAM (continued)

ORCA Series 4 FPGAs

CKW

CSW

AW

D

BW

CKWPL

CKWPH

CSWSU

CSWH

AWSU

AWH

c

DSU

DH

d

BWSU

BWH

AR a

Q

a

b

AQH

b

c

AQ

c

CKWQ

d

Figure 21. EBR Read and Write Cycles with Write Through

0308 (F)

Table 10. FIFO Signals

Port Signals

I/O

AR(1:0)[9:0]

I

AW(1:0)[9:0]

I

FF

O

PFF

O

PEF

O

EF

O

D0[17:0]

I

D1[17:0]

I

CKW[0:1]

I

CKR[0:1]

I

CSW[1:0]

I

CSR[1:0]

I

RESET

I

Q0[17:0]

O

Q1[17:0]

O

Function

Programs FIFO flags. Used for partially empty flag size.

Programs FIFO flags. Used for partially full flag size.

Full flag.

Partially full flag.

Partially empty flag.

Empty flag.

Data inputs for all configurations.

Data inputs for 256 x 36 configurations only.

Positive-edge write port clock. Port 1 only used for 256 x 36 configurations.

Positive-edge read port clock. Port 1 only used for 256 x 36 configurations.

Active-high write enable. Port 1 only used for 256 x 36 configurations.

Active-high read enable. Port 1 only used for 256 x 36 configurations.

Active-low. Resets FIFO pointers.

Data outputs for all configurations.

Data outputs for 256 x 36 configurations.

Lucent Technologies Inc.

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